Variable Gain Amp

Advanced Information SVG-2066 / SVG-2066Z Product Description Sirenza Microdevices’ SVG-2066 is an IC based 6-bit digital 31.5dB range attenuator cascaded with a linear class A amplifier in a low-cost surface-mountable 6x6 QFN plastic package. This product is specifically designed as a high linearity variable gain amplifier for infrastructure equipment that can be used in either the RF transmit or RF receive path. It features both parallel or serial programmability, programmable power up states, latchable parallel control, 3V or 5V combatible logic and robust Class 1B ESD. The SVG2066 features configurable pin I/O’s for optimizing the part over application specific bands. 500MHz - 2200MHz 6-Bit Variable Gain Amp Pb RoHS Compliant & Green Package 6mm x 6mm QFN Package Product Features Functional Block Diagram Serial or Parallel Select S-P VDD 2 Bit Power Up State Programming U1 U2 Serial Interface DATA CLK LE VCC RFIN RFOUT • • • • • • • • • • • • • P1dB = 25dBm @ 2140MHz OIP3 Typical 41dBm @ 2GHz Gain = 15dB at 850MHz 31.5dB Attenuation range in 0.5dB steps Serial or Parallel Controlled Optional Latched Parallel Control Programmable Power Up States Immune to Latch-Up Positive Supply Voltage 3V or 5V Logic Compatible www.DataSheet4U.com Applications CDMA, W-CDMA Tx and Rx GSM, EDGE Tx and Rx High Performance VGA applications Unit MHz dBm Min. 500 24 23.5 25 15 9.5 11 39 39 41 5.9 6.9 9 9 12 12 320 100 115 70 130 7.9 13.5 Typ. Max. 2200 P0.5 P1 P2 P4 P8 P16 6-Bit Parallel Interface Key Specifications Symbol fO P1dB S21 IP3 Parameters: Test Conditions, App circuit page 4 Z0 = 50Ω, VCC = 5.0V, Vdd=3V, I = 115mA, TL= 30ºC Frequency of Operation Output Power at 1dB Compression – 850MHz Output Power at 1dB Compression – 2.14GHz Small Signal Gain – 850MHz @ 0dB state Small Signal Gain – 2.14GHz @ 0dB state Third Order Intercept (Pout = 9dBm per tone) - 850MHz Third Order Intercept (Pout = 9dBm per tone) - 2.14GHz Noise Figure at 850 MHz @ 0 dB state Noise Figure at 2140 MHz @ 0 dB state Input Return Loss 850-2200 MHz ( 0dB attenuation ) Output Return Loss 850-2200MHz ( 0dB attenuation ) 10%/90% Settling time Current (Vcc = 5V,Vdd=3v) Thermal Resistance (junction - lead) dB dBm NF IRL ORL Ts Icq Rth, j-l dB dB nS mA ºC/W The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Specification continued Symbol ERR DYNR FCLK VDD IDD LH LL ILEAK Parameters: Test Conditions Z0 = 50Ω, VCC = 5.0V,Vdd=3V Iq = 115mA Atten setting accuracy any state (500MHz-2200MHz) Attenuation dynamic range Serial Data Clock Frequency Drain voltage of Attenuator Drain Supply Current Digital Logic High Digital Logic Low Digital Logic Leakage Unit dB dB MHz V uA V V uA 0.7xVDD 0 2.7 3.0 40 30.3 Min. Typ. +/- 0.2 31.5 Max. +/- (0.2+3% Atten setting) 32.7 20 3.3 100 VDD 0.3xVDD 1 Absolute Maximum Ratings Parameters VCC Bias Current (IC) VCC Bias Voltage Power Dissipation Drain Voltage (VDD) Voltage on any Digital Input Operating Lead Temperature (TL) Max RF Input Power Storage Temperature Range Operating Junction Temperature (TJ) ESD Human Body Model -40 -0.3 -0.3 -40 MIn Max 220 8 1.5 4.0 VDD+0.3 +85 21 +150 +150 500 Unit mA V W V V ºC dBm ºC ºC V Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation the device voltage and current must not exceed the maximum operating values specified in the table on page one. Bias conditions should also satisfy the following expression: IDVD < (TJ - TL) / RTH’ j-l Digital Interfacing: Serial or Parallel Mode Selection The SVG-2066 can be controlled with either a serial or parallel interface. The S-P bit selects the mode: S-P=low for parallel mode and S-P=high for serial mode. Parallel Mode Operation For latched parallel interfacing the LE line should be held low while changing attenuation state control logic P0.5 thru P16. To load data pulse LE from low to high and to low again. See Figure 1 and Table 1 on the next page for the parallel mode timing diagram and specifications. For direct parallel mode operation the LE line should be held high and the attenuation state is directly loaded when the parallel line logic changes. The truth table for parallel operation is shown in Table 2. Serial Mode Operation Three CMOS compatible signals control the attenuator in this mode: DATA, CLK and LE. When LE is high the latch is enabled and data in the serial shift register gets loaded. When the LE is low the data in the shift register is latched. Refer to Figure 2 for the timing diagram and Table 3 for the timing specifications. Power up State Programming At power up in serial mode the six control bits are set to the values available on the six parallel inputs P0.5 thru P16 (see Table 2). For parallel mode the power up state is set with the two bit word defined by U1 and U2. See the truth table in Table 4. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Figure 1: Parallel Mode Timing Diagram (S-P=0) LE Table 2: Parallel Mode Truth table (S-P=0) Attenuation State Reference 0.5 dB 1 dB P0.5 0 1 0 0 0 0 0 1 P1 0 0 1 0 0 0 0 1 P2 0 0 0 1 0 0 0 1 P4 0 0 0 0 1 0 0 1 P8 0 0 0 0 0 1 0 1 P16 0 0 0 0 0 0 1 1 Data P0.5 thru P16 2 dB 4 dB 8 dB 16 dB TD5 TD6 TD7 31.5 dB Table 1: Parallel Mode Timing Specifications (S-P=0) Parameter LE minimum pulse width Delay set up time before rising LE edge Data hold after falling edge of LE Symbol TD6 TD5 TD7 Unit nS nS nS Min 10 10 10 Max Figure 2: Serial Mode Timing Diagram (S-P=1) LE Table 3: Serial Mode Timing Specifications Parameter Serial data delay before clock rising edge Serial data hold after clock falling edge Symbol TD1 TD2 TD3 TD4 FCLK TCLKH TCLKL Unit nS nS nS nS MHz nS nS 30 30 Min 10 10 10 30 20 Max CLK LE delay after last clock falling edge LE minimum pulse width Serial data clock freq DATA MSB 16dB 8dB 4dB 2dB 1dB LSB 0.5dB Serial clock high time Serial clock low time TD3 TD1 TD2 TD4 Table 4: Power Up Truth Table for Parallel Mode (S-P=0) Attenuation State Reference 8 dB 16 dB 31 dB Defined by P0.5 Thru P16 LE 0 0 0 0 1 U1 0 1 0 1 Not Applicable U2 0 0 1 1 Not Applicable Note: Serial mode power up (S-P=1) state is defined by the parallel input logic shown in Table 2. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-104432 Rev 3 Advanced Information SVG-2066 500MHz-2200MHz 6-Bit VGA Pin Out Description Pin # 2,3,20,26,28 1,7,8,10,16, 21,23,24,25,30 4 5 6 9 11 12 13 14 15 17 18 19 22 27 29 31 32 33 34, 35 36 37 38 39 40 EPAD Label N/C GND RFIN J1 ATIN P8 P4 P2 P1 P0.5 P16 ATOUT J2 J3 AMPIN RFOUT VCC Data CLK LE U1 / U2 J5 J4 VDD S-P VSS GND Description These are unused pins and not wired inside the package. May be grounded or connected to adjacent pins. Pins are internally grounded RF input pin. Connects to 100pF cap inside package. Jumper this pin on the PC board to the attenuator input (ATIN) pin #6. Connects to 100pF cap inside package. Attenuator input pin Parallel interface attenuation control bit 8 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. Parallel interface attenuation control bit 4 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. Parallel interface attenuation control bit 2 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. Parallel interface attenuation control bit 1 dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. Parallel interface attenuation control bit 0.5dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. Parallel interface attenuation control bit 16dB. When in serial mode P0.5, P1, P2, P4, P8 and P16 logic dictate power up state. Attenuator output pin. Jumper this pin to the attenuator output pin (ATOUT). Connects to 100pF cap inside package. Connect this pin to the amplifier input pin (AMPIN) with the appropriate AMPIN impedance matching Amplifier input pin. Internally connected to base of amplifier (~1.3V) Amplifier RF output pin. Internally connected to 5V. Not matched to 50 ohm. Use appropriate matching circuit. Power Supply pin to Amplifier. Apply 5.0V to this pin. Serial interface data input. Serial interface clock input. Latch enable input. Parallel mode can also be latch enabled with this pin. Parallel mode power-up state logic bits. 0/0 = 0dB, 1/0 = 8dB, 0/1=16dB, 1/1=31dB Jumper this pin to GND on the PC board. Connects to 1000pF cap inside package. Jumper this pin on PC board to VDD pin 38. Connects to 1000pF bypass cap inside package. Power supply pin to Digital Attenuator. Apply 2.7-3.3V to this pin. May be set from another voltage with a voltage divider (pulls 40uA typ, 100uA max) Serial or parallel mode select. Logic low for parallel mode. Logic high for serial mode. Negative supply voltage or GND Exposed area on the bottom side of the package . GND with vias as shown