N-CHANNEL POWER MOSFET

STW14NM50 N-CHANNEL 550V @ Tjmax - 0.32Ω - 14A TO-247 MDmesh™ MOSFET Table 1: General Features TYPE STW14NM50 s s s s Figure 1: Package RDS(on) < 0.35 Ω ID 14 A VDSS (@Tjmax) 550 V s s TYPICAL RDS(on) = 0.32 Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE RATED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTORING YIELDS TO-247 DESCRIPTION The MDmesh™ is a new revolutionary MOSFET Figure 2: Internal Schematic Diagram technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizonwww.DataSheet4U.com tal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprierati strip technique yields overall dynamic performance that is significantly better than that of similar completition’s products. APPLICATIONS The MDmesh™ family is very suitablr for increase the power density of high voltage converters allowing system miniaturization and higher efficiencies. Table 2: Order Codes SALES TYPE STW14NM50 MARKING W14NM50 PACKAGE TO-247 PACKAGING TUBE Rev. 5 July 2004 1/9 STW14NM50 Table 3: Absolute Maximum ratings Symbol VGS ID ID IDM (1) Parameter Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value ±30 14 8.8 56 175 1.28 6 –65 to 150 150 Unit V A A A W W/°C V/ns °C °C PTOT dv/dt Tstg Tj (•)Pulse width limited by safe operating area (*)Limited only by maximum temperature allowed (1)ISD ≤14A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. Table 4: Thermal Data Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.715 30 300 °C/W °C/W °C Table 5: Avalanche Characteristics Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value 12 400 Unit A mJ ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On /Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125°C VGS = ± 30 V VDS = VGS, ID = 250 µA VGS = 10 V, ID = 6 A 3 4 0.32 Min. 500 1 10 ± 100 5 0.35 Typ. Max. Unit V µA µA nA V Ω 2/9 STW14NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (1) Ciss Coss Crss COSS eq (3). RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Gate Input Resistance Test Conditions VDS > ID(on) x RDS(on)max, ID = 6A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 5.2 1000 180 25 90 1.6 Max. Unit S pF pF pF pF Ω VGS = 0 V, VDS = 0 to 400 V f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain VDD = 250 V, ID = 6 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15) VDD = 400 V, ID = 12 A, VGS = 10 V (see Figure 18) td(on) tr td(off) tf Qg Qgs Qgd Turn-on Delay Time Rise Time Turn-off-Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge 20 10 19 8 28 8 15 38 ns ns ns ns nC nC nC Table 8: Source Drain Diode Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 12 A, VGS = 0 ISD = 12 A, di/dt = 100 A/µs VDD = 100V (see Figure 16) ISD = 12 A, di/dt = 100 A/µs VDD = 100V, Tj = 150°C (see Figure 16) 270 2.23 16.5 340 3 18 Test Conditions Min. Typ. Max. 14 56 1.5 Unit A A V ns µC A ns µC A (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. (3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/9 STW14NM50 Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/9 STW14NM50 Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Dource-Drain Diode Forward Characteristics 5/9 STW14NM50 Figure 14: Unclamped Inductive Load Test Circuit Figure 17: Unclamped Inductive Wafeform Figure 15: Switching Times Test Circuit For Resistive Load Figure 18: Gate Charge Test Circuit Figure 16: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/9 STW14NM50 TO-247 MECHANICAL DATA mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620 DIM. A A1 b b1 b2 c D E e L L1 L2 øP øR S 7/9 STW14NM50 Table 9: Revision History Date 05-July-2004 Revision 5 New Stylesheet. Description of Changes The document change from “PRELIMINARY” to “COMPLETE”. 8/9 STW14NM50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. 9/9