standard mobile imaging architecture (SMIA) decoder deserializer

www.DataSheet4U.com STSMIA832 1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Feature summary s Sub-low voltage differential signaling inputs: VID = 100mV MIN. with RT = 100Ω, CL = 10pF High signaling rate: fIN = 650 Mbps MAX (D+,D-,STRB+,STRB-) fOUT = 82 MHz MAX (CLK) fOUT = 82 Mbps MAX (for each data line D1-D8) Very high speed strobe to clock: tpLH~tpHL=5.2ns (TYP) at VDD=2.8V; VL=1.8V Operating voltage range: VDD(OPR) = 2.65V to 3.6V VL(OPR) =1.65V to 1.95V Symmetrical output impedance (D1-D8, HSYNC, V-SYNC, CLK): IIOHI=IOL=4mA (MIN) at VDD=2.65V;VL=1.8V Low power dissipation (DISABLED: EN=Gnd): ISOFF = IDD + IL = 10 µA (Max) SMIA specification compliant CLASS 0 and CLASS 1,2 supported (config by CLASS_SEL) CMOS logic input threshold (EN, SYNC_SEL, CLASS_SEL): VIL = 0.3xVL; VL = 1.65V to 1.95V VIH = 0.7xVL; VL = 1.65V to 1.95V 3.6V tolerant on inputs (EN, SYNC_SEL, CLASS_SEL) 32 BIT synchronization codes (SOF, EOF, SOL, EOL) Leadfree µTFBGA package (RoHS Restriction of hazardous substances) s µTFBGA25 s Description The STSMIA832 receiver converts the subLVDS clock/datastream (up to 650 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/LVTTL. The device recognizes the SMIA 32 bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 82 MHz) is transmitted in parallel with data. Output data are rising-edge strobes. This chipset is an ideal means to link mobile camera modules to Baseband processors. In order to minimize static current consumption, it is possible to shut down the device when the interface is not being used by a power-down (EN) pin that reduces the Maximum Current Consumption to 10 µA making this device ideal for portable applications like Mobile Phone and Portable Battery Equipment. A configurable input (Class_Sel) is provided to select different CLASS (0 or 1,2) mode inside the SMIA STD specifications. The STSMIA832 is offered in a µTFBGA package to optimize PCB space. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity from transient excess voltage. The STSMIA832 is characterized for operation over the commercial temperature range -40°C to 85°C. s s s s s s s s s Order codes Part number STSMIA832TBR May 2006 Temperature Range -40 to 85 °C Package µTFBGA25 3x3mm (TAPE & REEL) Rev. 2 Packaging 3000 parts per reel 1/23 www.st.com 23 STSMIA832 Contents 1 2 Schematic diagram ......................................... 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 Pin descriptions for reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Supplementary notes: SMIA specification . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power saving at the inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching off digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disabling the outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4 5 6 7 8 9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Frame structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 STSMIA832 Schematic diagram 1 Figure 1. Schematic diagram Simplified application block diagram Figure 2. Block diagram 3/23 Pin configuration STSMIA832 2 Figure 3. Pin configuration Pin connections (top through view - bumps are on the other side) Table 1. PlN N° D5 E5 D4 D3 D2 D1 E1 C3 A2, A1 A5, A4 B3 E3 C2 B2 E2, E4 A3, B1 B5 C1, C5 B4 C4 Pin description SYMBOL D1 D2 D3 D4 D5 D6 D7 D8 D+, DSTRB+, STRBEN CLK H-SYNC V-SYNC GND GND VDD VL SYNC_SEL CLASS_SEL Decoder output (LSB) Decoder output Decoder output Decoder output Decoder output Decoder output Decoder output Decoder output (MSB) Differential data receiver inputs Differential strobe receiver inputs (Class_Sel = VL) Differential clock receiver inputs (Class_Sel = GND) Receivers enable input Clock output Horizontal sync output Vertical sync output Ground (Digital I/O reference) Ground (Analog subLVDS part) Core supply voltage Digital I/O supply voltage Select sync input Select CLASS input NAME AND FUNCTION 4/23 STSMIA832 Pin configuration 2.1 Pin descriptions for reference: (D+, D-, STRB+, STRB-) Differential subLVDS data and strobe inputs to the receiver from the camera sensor interface. The signals operate at 150mV typical differential voltage levels and a common mode voltage of 900mV. The operating data rate is 650Mbps maximum. Depending on the CLASS_SEL pin selection mode, Data/Clock signaling or Data/Strobe signaling modes are activated. D1-D8, CLK STSMIA832 output data and clock lines. Parallel 8 bits of CMOS/LVTTL data is output at a maximum data rate of 82Mbps per line. Output LVTTL clock is transmitted in parallel with the data at 82MHz Max. SYNC-SEL The Horizontal Sync and Vertical Sync signals are extracted from the data stream before transmitting data on the parallel output D1-D8 if the device is working in ENABLED SYNC mode (SYNC_SEL = VL). If the device is working in DISABLED SYNC mode (SYNC_SEL = GND) the sync codes are not extracted from the data stream and the embedded Sync codes are transmitted along with the data on the parallel output. This allows for two modes of functioning, formatted and unformatted transmission of data on the data lines based on the selection by the Baseband processor. The main function table lists the functions for various combinations of SYNC_SEL pin and EN pin. CLASS-SEL The device embeds all functions forecast inside the SMIA Standard. STRB+ and STRBsignals are considered STROBE Signals when the device is working in HIGH CLASS mode (CLASS_SEL = VL). If the device is working in LOW CLASS mode (CLASS_SEL = GND) the STRB+ and STRB- inputs change their strobe functionality to CLOCK in order to be compliant with SMIA CLASS 0. In Class 0 mode of operation, data is read on the rising edge only. This allows for two modes of functioning, Clocked and Strobed transmission according to different applications and provides high flexibility to configure the final application in different Baseband processors. H-SYNC, V-SYNC In the ENABLED SYNC mode, the parallel data on D1-D8 is accompanied by the Horizontal and Vertical Sync signals on the H-SYNC and V-SYNC pins and together they are used to reconstruct the image frame. The H-SYNC and V-SYNC are generated by extracting the SMIA 32-bit Synchronization codes (SOF, EOF, SOL, EOL) on the serial input data stream. EN Enable pin is to enable the Power-Down Mode. This mode enables the shutting down of the device when the interface is not in use. The maximum current consumption can be reduced to 10 µA. This provision makes this device suitable for portable applications like Mobile phones or Portable Battery Equipment. 5/23 Pin configuration STSMIA832 VDD, VL Both the Camera Sensor module and the Baseband processor interface operate at VL = 1.8V. The subLVDS receiver core operating voltage is VDD = 2.8V typical. 2.2 Supplementary notes: SMIA specification The Standard Mobile Imaging Architecture (SMIA) specification defines an interface between the digital camera module and mobile phone engine. It defines a standard data transmission and control interface between transmitter (camera module) and receiver (mobile phone engine). The data transmission interface (referred to as CCP2) is a unidirectional differential serial interface with data and clock/strobe signals. The physical layer of CCP2 is based on signaling scheme called SubLVDS, which is current mode differential low voltage signaling method modified from the IEEE 1596.3 LVDS standard for reduced power consumption. STSMIA832 operates in a data/strobe signaling mode. The use of data-strobe coding together with SubLVDS enables the use of high data rates with low EMI. Data/Clock signaling Data is a differential output from camera module. Data format is in most of cases bytewise (i.e. on 8-bit boundary) least significant bit (LSB) first. When nothing is being transferred, the DATA lines remain high, except in power shutdown. Figure illustrates the bytewise LSB first transmission.. Figure 4. Data clock signaling Clock is a differential signal, output from camera module. The receiver reads the data on rising edge of the CCP_CLK. The clock signal may be free running or gated. For most cases free running clock is preferred due to simpler implementation in the transmitting end. However, in some cases gated clock may be better solution. If gated transmission clock is used, clock remains high when