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STK14C88
32Kx8 AutoStore nvSRAM DESCRIPTION
The Simtek STK14C88 is a 256Kb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is the highest performance, most reliable non-volatile memory available.
FEATURES
• 25, 35, 45 ns Read Access & R/W Cycle Time • Unlimited Read/Write Endurance • Automatic Non-volatile STORE on Power Loss • Non-Volatile STORE Under Hardware or Software Control • Automatic RECALL to SRAM on Power Up • Unlimited RECALL Cycles • 1 Million STORE Cycles • 100-Year Non-volatile Data Retention • Single 5V ± 10% Power Supply • Commercial, Industrial, Military Temperatures • 32-Pin 300 mil SOIC (RoHS-Compliant) • 32-pin CDIP and LCC Packages
BLOCK DIAGRAM
VCCX Quantum Trap 512 x 512 VCAP
A5 A6 A7 A8 A9 A11 A12 A13 A14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
POWER CONTROL
ROW DECODER
STORE STATIC RAM ARRAY 512 x 512 RECALL STORE/ RECALL CONTROL HSB
INPUT BUFFERS
COLUMN I/O COLUMN DEC
SOFTWARE DETECT
A0 - A13
A0 A1 A2 A3 A4 A10
G E W
This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status.
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Document Control #ML0014 Rev 0.3 February 2007
STK14C88
PIN CONFIGURATIONS
VCAP A14 A12 A7 A6 A5 A4 A3 NC A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCCX HSB W A13 A8 A9 A11 G NC A10 E DQ7 DQ6 DQ5 DQ4 DQ3
32-Pin 450 mil LCC
32-Pin 300 mil SOIC 32-Pin 300 mil CDIP
PIN DESCRIPTIONS
Pin Name A14-A0 DQ7-DQ0 E W G VCCX HSB Input I/O Input Input Input Power Supply I/O I/O Description Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array Data: Bi-directional 8-bit data bus for accessing the nvSRAM Chip Enable: The active low E input selects the device Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. Power: 5.0V, ± 10% Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. Ground
VCAP VSS
Power Supply Power Supply
Document Control #ML0014 Rev 0.3 February, 2007
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STK14C88
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC1b PARAMETER MIN Average VCC Current MAX 97 80 70 3 10 2 30 25 22 1.5 ±1 ±5 2.2 VSS – .5 2.4 0.4 0.4 0 70 - 40/-55 VCC + .5 0.8 2.2 VSS – .5 2.4 0.4 0.4 85/125 INDUSTRIAL/ Military MIN MAX 100 85 70 3 10 2 31 26 23 1.5 ±1 ±5 VCC + .5 0.8 mA mA mA mA mA mA mA mA mA mA μA μA V V V V V °C UNITS
(VCC = 5.0V ± 10%)e
NOTES
tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns All Inputs Don’t Care, VCC = max W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels All Inputs Don’t Care tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs All Inputs IOUT = – 4mA except HSB IOUT = 8mA except HSB IOUT = 3mA
ICC2c ICC3
b
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical Average VCAP Current during AutoStore Cycle Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic “1” Voltage Input Logic “0” Voltage Output Logic “1” Voltage Output Logic “0” Voltage Logic “0” Voltage on HSB Output Operating Temperature
ICC4c ISB1d
ISB2d IILK IOLK VIH VIL VOH VOL VBL TA
Note b: Note c: Note d: Note e:
ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms OUTPUT 255 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
CAPACITANCE
SYMBOL CIN COUT
f
(TA = 25°C, f = 1.0MHz)
MAX 5 7 UNITS pF pF CONDITIONS ΔV = 0 to 3V ΔV = 0 to 3V
PARAMETER Input Capacitance Output Capacitance
Note f:
These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
Document Control #ML0014 Rev 0.3 February 2007
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STK14C88
SRAM READ CYCLES #1 & #2
SYMBOLS NO. #1, #2 1 2 3 4 5 6 7 8 9 10 11 tELQV tAVAV
g
(VCC = 5.0V ± 10%)e
STK14C88-25 PARAMETER STK14C88-35 MIN MAX 35 35 25 10 5 5 10 0 10 0 25 0 35 0 13 0 45 5 5 13 0 15 35 15 5 5 15 45 45 20 STK14C88-45 UNITS MIN MAX 25 25 MIN MAX 45 ns ns ns ns ns ns ns ns ns ns ns
Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby
tAVQVh tGLQV tAXQXh tELQX tEHQZi tGLQX tGHQZi tELICCHf tEHICCLf
Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note h: I/O state assumes E and G < VIL and W > VIH; device is continuously selected. Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT)
DATA VALID
3 tAVQV
SRAM READ CYCLE #2: E Controlledg
2 tAVAV ADDRESS 6 tELQX 7 tEHQZ 1 tELQV 11 tEHICCL
E
G 8 tGLQX DQ (DATA OUT) 10 tELICCH
ACTIVE
4 tGLQV
9 tGHQZ
DATA VALID
ICC
STANDBY
Document Control #ML0014 Rev 0.3 February, 2007
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STK14C88
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ
i, j
(VCC = 5.0V ± 10%)e
STK14C88-25 PARAMETER STK14C88-35 MIN 35 25 25 12 0 25 0 0 10 5 5 13 5 MAX STK14C88-45 UNITS MIN MAX MIN 45 30 30 15 0 30 0 0 15 MAX ns ns ns ns ns ns ns ns ns ns 25 20 20 10 0 20 0 0
#2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
tWHQX
Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be ≥ VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledk, l
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
Document Control #ML0014 Rev 0.3 February 2007
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STK14C88
HARDWARE MODE SELECTION
E H L L X W X H L X HSB H H H L A13 - A0 (hex) X X X X Not Selected Read SRAM Write SRAM Nonvolatile STORE MODE I/O Output High Z Output Data Input Data Output High Z POWER Standby Active Active lCC2 m t NOTES
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises.
HARDWARE STORE CYCLE
SYMBOLS NO. Standard 22 23 24 25 26 tSTORE tDELAY tRECOVER tHLHX tHLBL Alternate tHLHZ tHLQZ tHHQX STORE Cycle Duration T
