32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM

www.DataSheet4U.com STK14C88-M 32K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM MIL-STD-883 FEATURES • Nonvolatile Storage without Battery Problems • 35ns and 45ns Access Times • “Hands-off” Automatic STORE with External 68µF Capacitor on Power Down • STORE to EEPROM Initiated by Hardware, Software or AutoStore™ on Power Down • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 100,000 STORE Cycles to EEPROM • 10-Year Data Retention in EEPROM • Single 5V + 10% Operation • Not Sensitive to Power On/Off Ramp Rates • No Data Loss from Undershoot • 32-Pad LCC and 32-Pin 300 mil CDIP Packages DESCRIPTION The Simtek STK14C88-M is a fast static RAM with a nonvolatile, electrically erasable PROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) can take place automatically on power down. A 68µF or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power from “hot swapping”. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be software controlled by entering specific read sequences. A hardware STORE may be initiated with the HSB pin. BLOCK DIAGRAM VCCX EEPROM ARRAY 512 x 512 VCAP PIN CONFIGURATIONS V CCX HSB A 14 V CAP A7 A 12 A 12 A7 3 4 30 29 W A 13 A8 A9 A 11 G NC A 10 E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 4 3 2 32 31 30 29 28 27 A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 32 300 mil DIP POWER CONTROL A6 A5 A4 A3 NC A2 5 6 7 8 9 10 11 12 13 14 15 16 28 27 26 25 24 23 22 21 20 19 18 17 A 6 5 6 7 8 9 10 11 12 0 1 W A 13 VCAP A 14 1 2 32 31 V CCX HSB A 5 A 4 A 8 A 9 ROW DECODER STORE STATIC RAM ARRAY 512 x 512 RECALL STORE/ RECALL CONTROL HSB A1 A0 DQ 0 DQ 1 DQ 2 V SS A 3 NC A 2 A 1 32 LCC 26 25 24 23 22 A 11 G NC A E DQ 10 A 0 DQ 13 21 14 15 16 17 18 19 20 7 DQ 1 DQ 2 3 DQ 4 DQ 5 VSS DQ INPUT BUFFERS COLUMN I/O COLUMN DEC SOFTWARE DETECT A0 - A13 PIN NAMES A0 - A14 DQ0 -DQ7 E W Address Inputs Data In/Out Chip Enable Write Enable Output Enable Hardware Store Busy (I/O) Power (+ 5V) Capacitor Ground A0 A1 A2 A3 A4 A10 G E W G HSB VCCX VCAP VSS April 1999 5-43 DQ 6 STK14C88-M ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS MILITARY SYMBOL ICC1b ICC2c ICC3b ICC4c ISB1d ISB2d IILK IOLK VIH VIL VOH VOL VBL TA PARAMETER MIN Average VCC Current Average VCC Current during STORE Average VCC Current at tAVAV = 200ns Average VCAP Current during AutoStore™ Cycle Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic “1” Voltage Input Logic “0” Voltage Output Logic “1” Voltage Output Logic “0” Voltage Logic “0” Voltage on HSB Output Operating Temperature – 55 2.2 VSS – .5 2.4 0.4 0.4 125 MAX 90 85 6 15 4 30 28 3 ±1 ±5 VCC + .5 0.8 mA mA mA mA mA mA mA mA µA µA V V V V V °C tAVAV = 35ns tAVAV = 45ns UNITS (VCC = 5.0V ± 10%)e NOTES All Inputs Don’t Care, VCC = max W ≥ (VCC – 0.2V) All Others Cycling, CMOS Levels All Inputs Don’t Care tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH E ≥ (VCC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs All Inputs IOUT = – 4mA except HSB IOUT = 8mA except HSB IOUT = 3mA Note b: Note c: Note d: Note e: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. ICC and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ) . 2 4 E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground. AC TEST CONDITIONS Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 5.0V 480 Ohms OUTPUT 255 Ohms CAPACITANCEf SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance (TA = 25°C, f = 1.0MHz) MAX 5 7 UNITS pF pF CONDITIONS ∆V = 0 to 3V ∆V = 0 to 3V 30 pF INCLUDING SCOPE AND FIXTURE Note f: These parameters are guaranteed but not tested. Figure 1: AC Output Loading April 1999 5-44 STK14C88-M SRAM READ CYCLES #1 & #2 SYMBOLS NO. #1, #2 1 2 3 4 5 6 7 8 9 10 11 tELQV tAVAVg tAVQVh tGLQV tAXQXh tELQX tEHQZ tGLQX tGHQZi tELICCH tEHICCL Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 35 0 13 0 45 3 5 13 0 15 35 35 15 3 5 15 PARAMETER MIN MAX 35 45 45 20 MIN MAX 45 ns ns ns ns ns ns ns ns ns ns ns STK14C88-35M (VCC = 5.0V ± 10%)e STK14C88-45M UNITS Note g: W and HSB must be high during SRAM READ cycles. Note h: Device is continuously selected with E and G both low. Note i: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledg, h tAVAV ADDRESS 5 3 2 tAVQV DATA VALID tAXQX DQ (DATA OUT) SRAM READ CYCLE #2: E Controlledg tAVAV ADDRESS tELQV E 6 tELQX 7 1 2 tEHICCL 1 1 tEHQZ G tGLQV 4 tGHQZ 9 8 tGLQX DQ (DATA OUT) tELICCH ACTIVE 10 DATA VALID ICC STANDBY April 1999 5-45 STK14C88-M SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZi, j tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 5 PARAMETER MIN 35 25 25 12 0 25 0 0 13 5 MAX MIN 45 30 30 15 0 30 0 0 15 MAX ns ns ns ns ns ns ns ns ns ns STK14C88-35M (VCC = 5.0V ± 10%)e STK14C88-45M UNITS Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be ≥ VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles. SRAM WRITE CYCLE #1: W Controlledk, l tAVAV ADDRESS tELWH E 14 19 12 tWHAX tAVWH 18 tAVWL 13 17 W tWLWH tDVWH 15 tWHDX DATA VALID 16 DATA IN tWLQZ 20 DATA OUT PREVIOUS DATA HIGH IMPEDANCE tWHQX 21 SRAM WRITE CYCLE #2: E Controlledk, l tAVAV ADDRESS tAVEL E 18 14 19 12 tELEH tEHAX tAVEH W tWLEH 15 13 17 tDVEH DATA IN DATA OUT HIGH IMPEDANCE DATA VALID tEHDX 16 April 1999 5-46 STK14C88-M HARDWARE MODE SELECTION E H L L X W X H L X HSB H H H L A13 - A0 (hex) X X X X 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63 MODE Not Selected Read SRAM Write SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output High Z Output Data Input Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z POWER Standby Active Active lCC2 m p NOTES L H H Active n, o, p lCC2 L H H Active n, o, p Note m: HSB store operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the store (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises. Note n: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note o: While there are 15 addresses on the STK14C88-M, only the lower 14 are used to control software modes. Note p: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. HARDWARE STORE CYCLE SYMBOLS NO. Standard 22 23 24 25 26 tSTORE tDELAY tRECOVER tHLHX tHLBL Alternate tHLHZ tHLQZ tHHQX PARAMETER (VCC = 5.0V ± 10%)e STK14C88-M UNITS MIN MAX 10 1 700 20 300 ms µs ns ns ns i, q i, q q, r NOTES STORE Cycle Duration Time Allowed to Complete SRAM Cycle Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy Note q: E and G low and W high for output behavior. Note r: tRECOVER is only applicable a