8K x 8 nvSRAM

STK10C68 STK10C68-M SMD#5962-93056 8K x 8 nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM FEATURES • 25ns, 35ns, 45ns and 55ns Access Times • STORE to Nonvolatile Elements Initiated by Hardware • RECALL to SRAM Initiated by Hardware or Power Restore • Automatic STORE Timing • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to Nonvolatile Elements (Industrial/Commercial) • 100-Year Data Retention (Industrial/Commercial) • Commercial, Industrial and Military Temperatures • 28-Pin DIP, SOIC and LCC Packages DESCRIPTION The Simtek STK10C68 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in Nonvolatile Elements. Data may easily be transferred from the SRAM to the Nonvolatile Elements (the STORE operation), or from the Nonvolatile Elements to the SRAM (the RECALL operation), using the NE pin. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) also take place automatically on restoration of power. The STK10C68 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. The STK10C68 features industry-standard pinout for nonvolatile RAMs. MIL-STD-883 and Standard Military Drawing (SMD #5962-93056) devices are available. BLOCK DIAGRAM QUANTUM TRAP 128 x 512 ROW DECODER PIN CONFIGURATIONS NE A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A5 A6 A7 A8 A9 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 STORE STATIC RAM ARRAY 128 x 512 RECALL VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 - LCC 28 - DIP 28 - SOIC INPUT BUFFERS COLUMN I/O COLUMN DEC STORE/ RECALL CONTROL PIN NAMES A0 - A12 W Address Inputs Write Enable Data In/Out Chip Enable Output Enable Nonvolatile Enable Power (+ 5V) Ground A0 A1 A2 A3 A4 A10 G NE E W DQ0 - DQ7 E G NE VCC VSS September 2003 1 Document Control # ML0006 rev 0.1 STK10C68 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS SYMBOL ICC b 1 (VCC = 5.0V ± 10%) COMMERCIAL MIN MAX 85 75 65 N/A 3 10 27 23 20 N/A 750 ±1 ±5 2.2 VSS – .5 2.4 0.4 0 70 –40/-55 VCC + .5 0.8 2.2 VSS – .5 2.4 0.4 85/125 INDUSTRIAL/ MILITARY MIN MAX 90 75 65 55 3 10 28 24 21 20 1500 ±1 ±5 VCC + .5 0.8 mA mA mA mA mA mA mA mA mA mA µA µA µA V V V V °C tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns All Inputs Don’t Care, VCC = max W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH tAVAV = 55ns, E ≥ VIH E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs All Inputs IOUT = – 4mA IOUT = 8mA UNITS NOTES PARAMETER Average VCC Current ICC c 2 3 Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical Average VCC Current (Standby, Cycling TTL Input Levels) ICC b ISB d 1 ISB d 2 VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic “1” Voltage Input Logic “0” Voltage IILK IOLK VIH VIL VOH VOL TA Note a: Output Logic “1” Voltage Output Logic “0” Voltage Operating Temperature Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 5.0V 480 Ohms OUTPUT 255 Ohms CAPACITANCEe SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance (TA = 25°C, f = 1.0MHz) MAX 8 7 UNITS pF pF CONDITIONS ∆V = 0 to 3V ∆V = 0 to 3V 30 pF INCLUDING SCOPE AND FIXTURE Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading September 2003 2 Document Control # ML0006 rev 0.1 STK10C68 SRAM READ CYCLES #1 & #2 SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZh tELICCHe tEHICCLd, e Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS PARAMETER Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 25 0 10 0 35 5 5 10 0 10 0 45 25 25 10 5 5 10 0 12 0 55 STK10C68-25 MIN MAX 25 35 35 15 5 5 12 0 12 STK10C68-35 MIN MAX 35 45 45 20 5 5 12 MIN (VCC = 5.0V ± 10%) STK10C68-45 MAX 45 55 55 25 STK10C68-55 MIN MAX 55 UNITS ns ns ns ns ns ns ns ns ns ns ns Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle. Note g: I/O state assumes E, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g tAVAV ADDRESS tAXQX DQ (DATA OUT) 5 3 2 tAVQV DATA VALID SRAM READ CYCLE #2: E Controlledf tAVAV ADDRESS tELQV E 6 tELQX 1 1 1 2 tEHICCL 7 tEHQZ G 8 tGLQX tGLQV 4 tGHQZ 9 DQ (DATA OUT) tELICCH ICC STANDBY 10 ACTIVE DATA VALID September 2003 3 Document Control # ML0006 rev 0.1 STK10C68 SRAM WRITE CYCLES #1 & #2 NO. 12 13 14 15 16 17 18 19 20 21 SYMBOLS #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZh, i tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW PARAMETER Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 5 STK10C68-25 MIN 25 20 20 10 0 20 0 0 10 5 MAX STK10C68-35 MIN 35 25 25 12 0 25 0 0 13 5 MAX MIN 45 30 30 15 0 30 0 0 14 5 (VCC = 5.0V ± 10%) STK10C68-45 MAX STK10C68-55 MIN 55 45 45 30 0 45 0 0 15 MAX UNITS ns ns ns ns ns ns ns ns ns ns Note i: Note j: If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be ≥ VIH during address transitions. NE ≥ VIH. SRAM WRITE CYCLE #1: W Controlledj tAVAV ADDRESS tELWH E 14 19 12 tWHAX 18 tAVWL tAVWH tWLWH 15 13 17 W tDVWH DATA IN tWLQZ DATA OUT PREVIOUS DATA HIGH IMPEDANCE 20 DATA VALID 16 tWHDX tWHQX 21 SRAM WRITE CYCLE #2: E Controlledj tAVAV ADDRESS tAVEL E 18 14 19 12 tELEH tEHAX tAVEH W tWLEH 15 16 13 17 tDVEH DATA IN DATA OUT HIGH IMPEDANCE DATA VALID tEHDX September 2003 4 Document Control # ML0006 rev 0.1 STK10C68 STORE INHIBIT/POWER-UP RECALL NO. 22 23 24 25 SYMBOLS Standard tRESTORE tSTORE VSWITCH VRESET Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level Low Voltage Reset Level PARAMETER (VCC = 5.0V + 10%) STK10C68 MIN MAX 550 10 4.0 4.5 3.6 UNITS NOTES µs ms V V k Note k: tRESTORE starts from the time VCC rises above VSWITCH. STORE INHIBIT/POWER-UP RECALL VCC 5V 24 VSWITCH 25 VRESET STORE INHIBIT POWER-UP RECALL 22 tRESTORE DQ (DATA OUT) POWER-UP RECALL BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH September 2003 5 Document Control # ML0006 rev 0.1 STK10C68 MODE SELECTION E H L L L L L L W X H L H L L H G X L X L H L H NE X H H L L L X MODE Not Selected Read SRAM Write SRAM Nonvolatile RECALLl Nonvolatile STORE No Operation POWER Standby Active Active Active ICC2 Active Note l: An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE. STORE CYCLES #1 & #2 NO. 26 27 28 29 30 31 32 tNLWL tELWL tWLEL SYMBOLS #1 tWLQXm tWLNHn #2 tELQX tELNH Alt. tSTORE tWC STORE Cycle Time STORE Initiation Cycle Time Output Disable Set-up to NE Fall tGHEL tNLEL Output Disable Set-up to E Fall NE Set-up Chip Enable Set-up Write Enable Set-up PARAMETER (VCC = 5.0V ± 10%) MIN MAX 10 20 0 0 0 0 0 UNITS ms ns ns ns ns ns ns tGHNL Note m: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V. Note n: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate the STORE initiation cycle. Note o: If E is low for any period of time in which W is high while G and NE are low