Single-Chip Set-Top Box Decoder with Hard Disk Drive and MP3

® CO n n SINGLE-CHIP SET-TOP BOX DECODER WITH MP3 AND HARD DISK DRIVE SUPPORT DATA SHEET The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver. To cover the needs of DVD-capable set-top boxes, STi5518 integration options include a CSS decryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPI interface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, the STi5518 is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and time-shifting. The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easy migration from the previous generation. The high level of integration in a single PQFP-208 package makes the STi5518 ideally suited for low-cost, high-volume set-top box applications. DMA channels arbitrator Programmable CPU memory interface MPEG-2 multichannel Dolby Digital® MP3, Alignment beep FID N IAL NT E STi5518 n n n n n n n Front-end interface (sector processor & DVD decryption) n n 2K instruction cache 2K data cache and 4K SRAM 2 UART, 2 SmartCard, PIO, 3PWM, MAFE interface IR blaster Diagnostics controller and system services MPEG2 video Sub-picture OSD & background n n • 2 UARTs, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers • Modem support • 44 bits of programmable I/O • IR transmitter/receiver. Professional toolset support • ANSI C compiler and libraries. 208 pin PQFP package. 7170179 D The information in this data sheet is subject to change without notice. w w w . at d sh a .c 4u et e om PAL/NTSC & SECAM 24 April 2001 www.DataSheet4U.com Integrated 32-bit host CPU up to 81 MHz • 2 Kbytes of Icache, 2 Kbytes of Dcache, and 4 Kbytes of SRAM configurable as Dcache. Audio decoder • 5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs • IEC60958 -IEC61937 digital output • SRS®/TruSurround® • DTS® digital out and MP3 decoding • Alignment beep for satellite dishes. Video decoder • Supports MPEG-2 MP@ML • Fully programmable zoom-in and zoom-out • NTSC to PAL conversion. DVD and SVCD subpicture decoder High performance on-screen display • 2 to 8 bits per pixel OSD options • Anti-flicker, anti-flutter and anti-aliasing filters. PAL/NTSC/SECAM encoder • RGB, CVBS, Y/C and YUV outputs with 10-bit DACs • Macrovision® 7.01/6.1 compatible (optional). Shared SDRAM memory interface • 1 or 2x16-Mbit, or 1x64-Mbit 125 MHZ SDRAM. Programmable CPU memory interface for SDRAM, ROM, peripherals... Front-end interface • DVD, VCD, SVCD and CD-DA compatible • Serial, parallel and ATAPI interfaces • Hardware sector filtering • Integrated CSS decryption and track buffer. Hardware transport-stream demultiplexor • Parallel/serial input • DES and DVB descramblers • 32 PID support. Integrated peripherals ST20 CPU IAL Table of contents NT IDE NF CO 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 STi5518 Architecture overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 Central processor MPEG video decoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 Audio decoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 IR transmitter/receiver - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 Modem analog front-end interface Memory subsystem Serial communication - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12 Front-end interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 On-chip PLL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 Diagnostic controller (DCU) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 Interrupt subsystem - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 PAL/NTSC/SECAM encoder - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 SmartCard interfaces - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13 PWM and counter module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 Parallel I/O module - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 Pin data - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15 Pin out - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15 Pin list sorted by function - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16 Pins sorted by pin number - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 20 Central processing unit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 Registers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28 Processes and concurrency Priority - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 29 Process communications - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 Timers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 Traps and exceptions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31 32 33 33 35 Trap groups - - - - - - - Events that can cause traps Trap handlers - - - - - - Restrictions on trap handlers 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 Instruction set - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36 Instruction cycles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36 Instruction characteristics - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 37 Instruction-set tables - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 38 Interrupt system - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 Interrupt controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 Interrupt vector table - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46 Interrupt handlers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 47 2/294 7170179 D STi5518 5.5 5.6 5.7 5.8 5.9 6 6.1 6.2 6.3 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 Interrupt latency - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48 Pre-emption and interrupt priority - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48 Restrictions on interrupt handlers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48 Interrupt level controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 49 Interrupt assignments - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50 CO FID N IAL NT E Memory map- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 51 Overview - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 51 Mapping - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 52 System memory use - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55 Memory - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 External memory - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 On-chip SRAM memory - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 - - - - - - - - - - - - - - - - - - - - locations 57 58 58 58 59 60 Caching - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56 Outline of operation - - - - - - - - Cache initialization - - - - - - - - - Cache subsystem control - - - - - - Data cache - - - - - - - - - - - - - Instruction cache - - - - - - - - - - Cacheable and non-cacheable memory 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Programmable CPU memory interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 63 Pin functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 64 Configuration list - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 68 External bus cycles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 70 DRAM - - - - - - - - - - - - - SDRAM - - - - - - - - - - - - SRAM or peripheral access cycles Wait - - - - - - - - - - - - - - Bank-width based address shifting 71 75 78 79 80 8.4 8.5 9 9.1 9.2 10 10.1 10.2 10.3 10.4 10.5 11 12 12.1 12.2 EMI configuration - - - - - - - - - - -