. . .
A TOP BOX / DVD BACKEND DECODER SET L TIWITH INTEGRATED HOST PROCESSOR N E FID N CO 32-BIT VL-RISC CPU ENHANCED - DES AND DVB DESCRAMBLERS
SUMMARY
STi5500
. . . .
- FAST INTEGER/BIT OPERATION AND VERY HIGH CODE DENSITY HIGH PERFORMANCE MEMORY/CACHE SUBSYSTEM - 2KBYTES INSTRUCTION CACHE, 2KBYTES SRAM, 2KBYTES DATA CACHE/SRAM - 160MBYTES/S BANDWIDTH COMBINED VIDEO AND AUDIO DECODER CORE - VIDEO DECODER FULLY SUPPORTS MPEG-2 MP@ML - MEMORY REDUCTION - PAL MP@ML IN 12MBITS - 2 TO 8 BIT PER PIXEL OSD OPTIONS - LETTERBOX (16:9) DISPLAY FORMAT - HORIZONTAL AND VERTICAL RESIZING FUNCTIONS - AUDIO DECODER SUPPORTS LAYERS 1 AND 2 OF MPEG, INTERFACE TO EXTERNAL DOLBY AC-3™ DECODER PAL/NTSC ENCODER - MACROVISION™ VERSION 7.01/6.1 COMPATIBLE - TELETEXT, AND CLOSED CAPTION - SIMULTANEOUS OUTPUT OF RGB, CVBS AND COMPONENT VIDEO HIGH PERFORMANCE SDRAM MEMORY INTERFACE - SUPPORTS 1 OR 2 16MBIT 100MHz SDRAMS - ACCESSIBLE BY MPEG DECODER, CPU AND DMAS - HIGH BANDWIDTH ACCESS FROM CPU ALLOWS HIGH PERFORMANCE OSD OPERATIONS PROGRAMMABLE MEMORY INTERFACE - 4 BANKS EACH 8/16 BITS WIDE - SU P PO R T F O R MI XE D ME MO R Y , PER I PH ERALS, DRAM AND POWER PC LINK INTERFACE - SERIAL INPUT - SUPPORTS DSS, DVB, AND DVD BITSTREAMS - 32 PIDS SUPPORTED
. . . . .
- 32 SI/PSI FILTERS OF 16 BYTES VECTORED INTERRUPTS - 8 PRIORITIZED LEVELS DMA ENGINES/INTERFACES - 2 UARTS, 1 I2C CONTROLLER, 3 PWM OUTPUTS, 3 TIMERS, 3 CAPTURE TIMERS - 24 BITS OF PIO SHARED WITH SERIAL INTERFACES - OS LINK INTERFACE - BLOCK MOVE DMA, 2 MPEG DMAS - TELETEXT INTERFACE PROFESSIONAL TOOLSET SUPPORT - ANSI C COMPILER AND LIBRARIES - INQUEST ADVANCED DEBUGGING TOOLS NON-INTRUSIVE DEBUG CONTROLLER - HARDWARE BREAKPOINTS - REAL TIME TRACE 208 PIN PQFP PACKAGE
DESCRIPTION The STi5500 is the first of a new generation of integrated multimedia decoder engines for set top box and DVD applications. It offers a high level of integration by reducing the complete set top box decoding chain from Transport Demux to PAL/NTSC Encoder onto one chip. At the same time it dramatically enhances CPU and Graphics performance, and cuts down total system memory cost.
PQFP208 (Plastic Quad Flat Pack) ORDER CODE : STi5500
October 1997
This is advance information on a new product now in development or undergoing evaluation. Detail are subject to change without notice. s
1/11
STi5500
NOT_TRST
DATA[15] 158
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
VDD PIO3[7] PIO2[0] GND PIO2[3] PIO2[4] PIO2[5] PIO2[7] PIO1[0] PIO1[2] PIO1[5] PIO1[6] PIO1[7] PIO4[7] PIO0[0] PIO0[3] PIO0[4] VDD GND PIO0[5] PIO0[6] PIO0[7] IRQ[0] IRQ[1] IRQ[2] BRM0 BRM1 BRM2 NOT_RST SDAV_CLK (PI394_CLK) SDAV_CLK (PI394_DATA) SDAV_DIR (PI394_CLK) OSC_IN VDD GND F_DATA F_B_BCLK F_P_CLK F_ERR NRSS_CLK NRSS_OUT NRSS_IN PCM_CLKOUT (A_C_STB) PCM_DATA (A_C_DATA) PCM_CLKIN LRCLK (A_WORD_CLK) A_C_REQ A_PTS_STB VDD GND NOTHSYNC ODD_OR_EVEN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
157
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137
DATA[14]
ADR[21]
ADR[20]
ADR[19]
ADR[18]
ADR[17]
ADR[16]
ADR[15]
ADR[14]
ADR[13]
ADR[12]
ADR[11]
ADR[10]
PIO3[6]
PIO3[5]
PIO3[4]
PIO3[3]
PIO3[2]
PIO3[1]
PIO3[0]
PIO1[4]
PIO1[3]
PIO4[6]
PIO4[5]
PIO4[4]
PIO4[3]
PIO4[2]
PIO4[1]
PIO4[0]
ADR[9]
ADR[8]
ADR[7]
ADR[6]
ADR[5]
ADR[4]
ADR[3]
ADR[2]
ADR[1]
L TIA I - PIN DESCRIPTION N I.1 - Pin Connections IDE F ON C
GND VDD
GND
GND
GND
TDO
TMS
TCK
TDI
VDD
VDD
VDD
DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] GND VDD DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] GND VDD N_PPC_MOD CPU_CLK (PPC_CLK) READY NOT_CSDXX DMAXFER READnotWRITE NOT_CAS1 GND VDD NOT_CAS0 NOT_RAS1 NOT_RAS0 NOT_CE3 NOT_CE2 NOT_CE1 NOT_OE NOT_WE1 NOT_WE0 GND VDD PIXCLK_27MHz OSD_ACTIVE AUXCLK DQ[15] DQ[14] DQ[13] DQ[12] GND VDD DQ[11] DQ[10] DQ[9] DQ[8] DQMU
STi5500
PQFP208 (Top View)
136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
100
101
102
103 GND
V_REF_DAC_RG
I_REF_DAC_RG
MEMCLKOUT
B_OUT
Y_OUT
GND
GND
V_REF_DAC_YC
I_REF_DAC_YC
GND
GND
NOT_SDRAS
NOT_SDCAS
NOT_SDCS[0]
NOT_SDCS[1]
NOT_SDWE
MEMCLKIN
VDDA_0
VDDA_1
G_OUT
R_OUT
C_OUT
CV_OUT
VSSA_0
VSSA_1
DQML
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[0]
AD[1]
AD[2]
AD[3]
DQ[0]
DQ[1]
DQ[2]
DQ[3]
DQ[4]
DQ[5]
DQ[6]
AD[10]
AD[11]
DQ[7]
VDD
VDD
VDD
VDD
VDD
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
2/11
5500-01.EPS
STi5500
Pin Name SUPPLIES 1, 18, 34, 49, 67, 75, 86, 95, VDD 102, 110, 119, 130, 139, 149, 159, 171, 184, 208 4, 19, 35, 50, 68, 77, 87, 96, GND 103, 111, 120, 131, 140, 150, 160, 172, 185, 200 53, 60 VDDA 54, 61 VSSA VIDEO OUTPUT INTERFACE 57 R_OUT 56 G_OUT 55 B_OUT 63 C_OUT 64 CV_OUT 62 Y_OUT 59 I_REF_DAC_RGB 66 I_REF_DAC_YCC 58 V_REF_DAC_RGB 65 V_REF_DAC_YCC 117 OSD_ACTIVE 118 PIXCLK_27MHz 51 NOTHSYNC 52 ODD_OR_EVEN AC-3/MPEG1-2 AUDIO OUTPUT INTERFACE 43 PCM_CLKOUT / A_C_STB 44 PCM_DATA / A_C_DATA 45 PCM_CLKIN 46 LRCLK / A-WORD_CLK 47 A_C_REQ 48 A_PTS_STB EXTERNAL INTERRUPTS 23, 25, 24 IRQ0-2 PROGRAMMABLE I/O 15, 16, 17, 20, 21, 22 PIO-0 [0, 3-7] 9, 10, 198, 199, 11, 12, 13 PIO-1 [0, 2-7] 3, 5, 6, 7, 8 PIO-2 [0, 3-5,7] 201-207, 2 PIO-3 [0-7] 191-197, 14 PIO-4 [0-7] JTAG INTERFACE 188 TCK 186 TDI 189 TDO 187 TMS 190 NOT_TRST SYSTEM USE 28 BRM2 27 BRM1_OR_BOOTFROMROM 26 29 116 BRM0_OR_OSLINK_SEL NOT_RST AUXCLK
L TIA II - PIN DESCRIPTION (continued) N I.2 - Pin List IDE F ON C
Type Power Supply Ground
Function
Analog Power Supply for DENC Analog Ground for DENC O O O O O O I I I I I/O I I/O I/O O O I/O O I I I I/O I/O I/O I/O I/O I I O I I O O/I O/I I O Red Output Green Output Blue Output Chroma Output Composite Video Output Luma Output DAC Current Reference DAC Current Reference DAC Voltage Reference DAC Voltage Reference OSD Active System Clock Input Horizontal Sync Vertical Sync (PCM Clock Out) or AC3 Data Strobe Data Out PCM Data Out or AC3 PCM CLock In From VCXO Left/Right Clock or AC3 Word Clock AC3 Data Request AC3 Audio PTS Strobe External Interrupts General Purpose IO General Purpose IO General Purpose IO General Purpose IO General Purpose IO Test Clock Test Data Input Test Data Input Test Mode Select Test Reset Modem Voltage Control VCXO Control Audio BRM or Bootfromrom During Reset VCXO Control Video BRM or Configure Oslink Pins Reset Auxilary Clock for Any Purpose 3/11
STi5500
Pin Name Type Function SDRAM INTERFACE 78-81, 69, 70, 71, 72, 73, AD[0:11] O SDRAM Address Bus 74, 82, 83 92, 93, 94, 97, 98, 99, 100, DQ[0:15] I/O SDRAM Data (Lower Byte) 101, 106, 107, 108, 109, 112-115 84, 85 NOT_SDCS0-1 O SDRAM Chip Selects 89 NOT_SDCAS O SDRAM CAS 88 NOT_SDRAS O SDRAM RAS 90 NOT_SDWE O SDRAM Write Enable 104 MEMCLKIN I SDRAM Memory Clock Input 76 MEMCLKOUT O SDRAM Memory Clock Output 91 DQML O DQ Mask Enable (Lower) 105 DQMU O DQ Mask Enable (Upper) ROM AND EXTERNAL MICROPROCESSOR 161-170, 173-183 ADR[1:21] I/O External Memory Address Bus 141-148, 151-158 DATA[0:15] I/O External Memory Data Bus 128 NOT_RAS1_OR_HOLDREQ O DRAM RAS or Bus Request to External Micro 136 READY O Hold off External Micro 133 READNOTWRITE_OR_DMAACK I/O DRAM R/W Strobe or DMA Acknowledge from External Micro 121, 122 NOT_WE[0:1] I/O Write Enable of SRAM 129 NOT_CAS0_OR_HOLDACK O/I DRAM CAS or Bus Grant from External Micro 132 NOT_CAS1_OR_NOT_DMAREQ O DRAM CAS or DMA Request (Ready) to External Micro 124-126 NOT_CE[1:3] O Chip Select for Banks 1 - 3 135 NOT_CS I Chip Select to Access SDRAM 137 PPC_CLK I Power PC System Clock 127 NOT_RAS0_OR_NOT_CE4 O DRAM RAS or Chip Select for Bank 0 134 DMAXFER I DMA Transfer Control from External Micro 138 NOT_PPC_MODE I Presence of Power PC 123 NOT_OE I/O Output Enable of RAM / ROM SDAV INERFACE 30 SDAV_CLK I/O Data Strobe / CLK 31 SDAV_DATA I/O Data Line 32 SDAV_DIR O Direction for Transmit Truefer Transmit, Pulse for Receive 33 OSC_IN I/O 49.152MHz Crystal Input NRSS INTERFACE 40 NRSS_CLK O NRSS Serial Clock 42 NRSS_IN I NRSS Serial Data Input 41 NRSS_OUT O NRSS Serial Data Output P1394 INTERFACE 30 P1394_CLK I/O Data Strobe / CLK 31 P1394_DATA I/O Data Line 32 P1394_P_CLK I/O Packet Clock
L TIA II - PIN DESCRIPTION (continued) N II.2 - Pin List (continued) IDE F ON C
4/11
STi5500
L TIA II - BLOCK DIAGRAM EN Block Figure 1 : General ID Diagram F ON C
ST20 CPU BLOCK MOVE DMA 2 MPEG DMAs INTERRUPT CONTROLLER
EMI LINK INTERFACE
MPEG AUDIO DECODER AC-3 I/F
2K INSTRUCTION CACHE
2 SMARTCARD INTERFACES (ASC)
2K DATA CACHE AND 2K SRAM MPEG VIDEO DECODER
OS LINK 2 UART 1 I2C PIO 3 PWM DIAGNOSTICS CONTROLLER AND SYSTEM SERVICES
PAL/NTSC ENCODER
5/11
5500-02.EPS
TELETEXT INTERFACE
STi5500
L TIA III - INTERNAL CIRCUIT DESCRIPTION N A general block diagram for the STi5500 is shown IDE F is Figure 1. N O offered by the ST20 32-bit microC The performance
core allows the following operations to be performed in software : 1 Device drivers for Video, Audio and Sub-picture Decoders 2 Audio/Video/Subpicture synchronisation 3 System management functions 4 Electronic program guide 5 Conditional access module The use of a 32-bit CPU enables advanced graphics routines to be employed for on-screen display functions, allowing fast turnaround system upgrades. III.1 - The ST20 32-bit CPU The ST20 micro-core family has been developed by SGS-THOMSON Microelectronics to provide the tools and building blocks to enable the development of highly integrated application-specific 32-bit devices at the lowest cost and fastest time to
