Convolutional Encoder Viterbi Decoder

www.DataSheet4U.com STEL-5269+512 Data Sheet STEL-5269+512 Convolutional Encoder Viterbi Decoder www.DataSheet4U.com R www.DataSheet4U.com FEATURES s CONSTRAINT LENGTH 7 s CODING RATES 1/2 AND 1/3 s THREE BIT SOFT-DECISION INPUTS IN SIGNED MAGNITUDE OR 2’s COMPLEMENT FORMAT s CODING GAIN OF 6.0 dB (AT 10–5 BER, RATE 1/3) s INDUSTRY STANDARD POLYNOMIALS G1 = 1718, G2 = 1338, G3 = 1458, s 512 Kbps DATA RATE (0° to 70° C) s CODING GAIN OF 5.2 dB (AT 10-5 BER, RATE 1/2) s LOW POWER CONSUMPTION s 44 PIN PLCC AND CLDCC PACKAGES s AVAILABLE TO MIL-STD 883C BLOCK DIAGRAM DATACLK DATAIN Q1 7-BIT SHIFT REGISTER Q2 Q3 Q4 Q5 Q6 Q7 ENCODER SECTION OSY MB "INV G2" SCRAMBLER AND 3:1 MUX D Q LATCH SEL A, B MODE ERATE ENLATCH RESET SCRAMBL OCLK ICLK DRDY ACK DRATE SYNC0 SYNC1 3 3 3 2 MODE SELECT AND CONTROL 2 SELECT (TO ALL REGS.) DECODER SECTION ADDRESS SEQUENCER AND CONTROL LOGIC STATE-METRIC RAM TRELLIS RAM ADDR G1D 2-0 G2D 2-0 G3D 2-0 SM2C "INV G2" DESCRAMBLER, BUFFER REG. & MUX. DAT A BRANCH METRIC AND ADD-COMPARESELECT LOGIC PATH HISTORY AND AUTO NODE-SYNC LOGIC DOUT SYNC SST0 SST1 MIS 3 www.DataSheet4U.com THRESH STEL-5269+512 2 www.DataSheet4U.com FUNCTIONAL DESCRIPTION Convolutional Encoding and Viterbi Decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. In satellite communication systems where transmitter power is limited, FEC techniques can reduce the required transmission power. The STEL-5269+512 is a specialized product designed to perform this specific communications related function. The encoder creates a stream of symbols which are transmitted at 2 (Rate 1/2) or 3 (Rate 1/3) times the information rate. This encoding introduces a high degree of redundancy which enables accurate decoding of information despite a high symbol error rate resulting from a noisy link. The STEL-5269+512 incorporates all the memories required to perform these functions. The STEL5269+512 is available in a 44-pin PLCC (plastic leaded chip carrier) and also in a ceramic leaded chip carrier (J-bend leads). A 256 Kbps version, the STEL-5269, is also available at a lower cost. ENCODER OPERATION The convolutional coder is functionally independent of the decoder. A single data bit is clocked into the 7-bit shift register on the rising edge of DATACLK. There are two modes of operation, controlled by the MODE input. When MODE is low the timing of the SEL A SEL B and ENLATCH signals determine , whether 2 or 3 symbol bits are generated for every data bit. When MODE is high the symbols are automatically generated sequentially every clock cycle. In this case, the state of ENRATE determines whether the device generates symbols for Rate 1/2 or Rate 1/3 operation. The symbols G1, G2, and G3 are generated from the modulo-2 sum (exclusive-OR) of the inputs to the 3 generators from the taps on the shift register. The 3 polynomials are 1718 (G1), 1338 (G2), and 1458 (G3). Example inputs are shown in the timing diagram for both rate 1/2 and rate 1/3 operation. PIN CONFIGURATION Package: 44 pin PLCC Thermal coefficient, θja = 40°C/W 4 4 4 4 4 6 5 4 3 2 1 4 3 2 1 0 7 8 9 10 11 12 13 14 15 16 17 1 1 2 2 22 2 2 2 2 2 8 9 0 1 23 4 5 6 7 8 0.653" ± 0.010" 39 38 37 36 35 0.690" 34 33 ± .005" 32 31 30 29 0.18" max. 0.017" ± 0.004" (2) 7 8 9 10 11 12 13 14 15 16 17 Package: 44 pin CLDCC Thermal coefficient, θja = 50° C/W 0.14" max. 4 4 4 4 4 6 5 4 3 2 1 4 3 2 1 0 39 38 37 36 35 0.690" 34 33 ± .010" 32 31 30 29 0.016" ± 0.004" (2) Top View 0.05" nom. (1) 0.05" nom. (1) 0.02" min. 1 1 2 2 22 2 2 2 2 2 8 9 0 1 23 4 5 6 7 8 0.653" ± 0.004" 0.045" nom. Notes: (1) Tolerances on pin spacing are not cumulative. (2) Dimensions apply at seating plane. (3) PLCC and CLDCC packages have different corners and may not fit into sockets designed for the other type. Universal sockets are available without alignment locators. www.DataSheet4U.com PIN CONNECTIONS 1 SYNC 2 VSS 3 ACK 4 DATACLK 5 DRDY 6 DATAIN 7 G3D0 8 G3D1 9 G3D2 10 MODE 11 VSS 12 13 14 15 16 17 18 19 20 21 22 MIS DOUT OSYMB G2D0 G2D1 G2D2 G1D0 G1D1 G1D2 ENLATCH VDD 23 24 25 26 27 28 29 30 31 32 33 VSS THRESH0 THRESH1 RESET DRATE SEL A THRESH2 VDD VSS I.C. ERATE 34 35 36 37 38 39 40 41 42 43 44 VSS SST1 SYNC1 SST0 SYNC0 SEL B SM2C ICLK OCLK SCRAMBL I.C. Note: I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias. 3 STEL-5269+512 www.DataSheet4U.com DECODER OPERATION INPUT SIGNALS RESET Asynchronous master Reset. A logic low on this pin will clear all registers on the STEL-5269+512 in both the encoder and decoder sections of the chip. RESET should remain low for at least 3 cycles of ICLK. DATACLK This is the encoder Shift Register Clock. A rising edge on this clock latches DATAIN into the encoder shift register. This signal should nominally be a square wave with a maximum frequency of 512 KHz. DATAIN This is the encoder input. The data present at this pin is latched into the encoder shift register on the rising edge of DATACLK. This signal should be stable at the rising edge of DATACLK. MODE The state of the MODE input determines the method of symbol sequencing in the encoder. When MODE is set low the sequencing is generated externally under the control of the SEL A and SEL B inputs, and when MODE is set high it is generated automatically. SEL A, SEL B When MODE is set low SEL A and SEL B select the encoded symbol, G1, G2 or G3, which will appear on the OSYMB pin on the next rising edge of ENLATCH according to the table: SEL A SEL B SYMBOL POLYNOMIAL 0 1 0 1 0 0 G1 G2 G3 1718 (11110012) 1338 (10110112) 1458 (11001012) The STEL-5269+512 is designed to accept symbols either synchronously or in a handshake mode. Symbols are latched into the decoder input registers on the falling edge of the DRDY input. ACK is returned by the decoder to indicate that the symbols have been accepted. The RATE input determines whether the decoder will operate in Rate 1/2 or Rate 1/3 mode. When operating at Rate 1/2 the G3 symbol is ignored by the decoder. For hard decision binary symbols the G1, G2, G3 symbol bits should be connected to pins G1D2, G2D2 and G3D2 respectively, and the other symbol input pins should be tied high (VDD). Three-bit soft decision symbols may be input in Signed Magnitude or Inverted Two’s Complement code, according to the setting of the code control pin, SM2C. The code should be set to Signed Magnitude when using hard decision data. A single decoded data bit is output for every set of input symbols. The data bit corresponding to a particular symbol set will be output after a delay of 42 symbols. Therefore, when using the STEL-5269+512 to decode blocks of data 42 additional dummy symbols and 42 DRDY signals need to be added to the data stream to flush the last 42 decoded data bits out of the decoder. Node synchronization (correctly grouping incoming symbols into G1, G2, and G3 sets) is inherent with many communication techniques such as TDMA and spread spectrum systems. If node synchronization is not an inherent property of the communications link then the internal auto node sync circuit can be used to do this. This is accomplished by connecting the node sync outputs (SST0 and SST1) to the node sync inputs (SYNC0 and SYNC1). The threshold for determining the out of sync condition is user selectable by means of the THRESH2-0 inputs. Alternatively, the SYNC0 and SYNC1 pins can be used with an external algorithm to achieve the same result. Further information on the theory of operation of Viterbi decoders may be obtained from text books such as "Error-Correcting Codes", by Peterson and Weldon (MIT Press), or "Error Control Coding", by Lin and Costello (Prentice-Hall). An alternative source of information is the many papers on this subject that have appeared in the IEEE transactions, such as "Convolutional Codes and their Performance in Communication Systems", by Dr. A. J. Viterbi, IEEE Trans. on Communications Technology, October 1971. When MODE is set high the symbol sequence is generated automatically and the SEL A and SEL B inputs are inactive. ERATE When MODE is high the Encoder Rate input determines whether symbols for Rate 1/2 (ERATE = 1) or Rate 1/3 (ERATE = 0) operation are generated. When MODE is low this input is inactive. SCRAMBL When the Scramble input is set high the G2 symbol generated at the encoder and the G2 symbol received at the decoder will be inverted. This ensures that the output symbol stream is not a string of zeroes when the input data stream is all zeroes, thereby making it easier for the demodulator to recover the clock information under these conditions. When SCRAMBL is set low the normal symbol stream is generated. www.DataSheet4U.com STEL-5269+512 4 www.DataSheet4U.com ENLATCH This is the encoder Output Latch Enable. The new symbol is clocked into the output latch and appears on the OSYMB pin on the rising edge of ENLATCH. When MODE is low the symbol selected will depend on the states of the SEL A and SEL B lines, which should be stable on the rising edge of ENLATCH. When MODE is high the symbol selection is internal, and the frequency of the ENLATCH signal should be 2 or 3 times the frequency of the DATACLK, depending on the rate selected. ICLK, OCLK System Clock. A crystal may be connected between ICLK and OCLK or a CMOS level clock may be fed into ICLK only. The clock frequency should be at least 70 times the data rate but no more than 36 MHz. DRATE The Decoder Rate input selects whether the decoder will read two symbols (DRATE set high) or three symbols (DRATE set low)) for every data bit decoded. During rate 1/2 operation the symbol G3 on inputs G3D2-0 is completely ignored by the decoder. G1D2-0, G2D2-0, G3D2-0 The three 3-bit soft decision symbols are connected to these inputs and loaded into the input registers on the falling edge of DRDY. The order in which the symbols are entered into the