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STEL-2060C/CR Data Sheet
STEL-2060C/CR
45 Mbps Viterbi Decoder
R
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FEATURES s 45 Mbps Operating Rate s Constraint Length K = 7
G1 = 1718 G2 = 1338
FUNCTIONAL DESCRIPTION
Convolutional encoding and Viterbi decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. The STEL-2060C is a specialized product designed to perform this specific communications related function. At the encoder a stream of symbols is created which introduces a high degree of redundancy. This enables accurate decoding of the information despite a high symbol error rate resulting from an impaired communications link. The STEL-2060C contains a K = 7 Viterbi Decoder. The data inputs can be in offset binary or offset signed-magnitude formats, with 3-bit soft decision. Auto node sync is provided for applications where symbol uncertainty can occur. Rate 2 /3, 3/4, 4/5, 5/6, 6/7 and 7/8 punctured signals can be decoded, as well as non-punctured, Rate 1/2, signals. The polynomials and puncturing patterns used are industry standards. Depuncturing logic is incorporated into the decoder to provide automatic depuncturing of received data at rates 2/3, 3/4 and 7/8 when the puncturing patterns supported by the device are used. A BER monitor is also provided in the device, along with a circuit for computing the mean value of the BER over an extended period. These circuits operate with punctured codes as well as unpunctured. The STEL-2060C incorporates a descrambler for signals scrambled with the “Invert G2” algorithm. (With this method the G2 symbols are logically inverted at the encoder. This provides a very effective level of scrambling for the purpose of avoiding long strings of ones or zeroes in the transmitted signal using BPSK modulation.)
s s s s s s s s s s s
Multiple Rates: Rate 1/2 as well as Punctured codes at Rates 2/3 through 7/8 Internal Depuncturing Capability at Rates 2 /3, 3/4 and 7/8 Multiple Devices can be Multiplexed to Give Higher Data Rates Optimized Interface to Operate with BPSK and QPSK Demodulators Auto Node Sync Capability Differential Decoder “Invert G2” Descrambler Internal BER Monitor and BER Measurement Circuit 5.2 dB Coding Gain @10-5 BER (R = 1/2) 100-pin PQFP Package 0.5 Micron CMOS Technology
BLOCK DIAGRAM
DSCRAM OBIN PARL LDG2 G1 G2
3 3 2
SYMBOL ALIGNMENT AND DEPUNCTURING CIRCUIT
BRANCH METRIC ASSIGNMENT
VITERBI DECODER (ACS)
PNCG1/G2 SYMCKIN DCLKIN SYNC RATE EXTSEL THRES H COUNT DDIF DATA ADDR WR RD CSEL RESET
8 3
TRACEBACK MEMORY NODE SYNC CONTROL AUTO OOS
3
TIMING AND CONTROL DATO ODCLK
8 8
DIFFERENTIAL DECODER
µP INTERFACE
BER MONITOR AND COUNTER
BERR G1ERR G2ERR INT
TO ALL REGISTERS
STEL-2060C
2
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PIN CONFIGURATION
Package: 100-pin HQFP Thermal coefficient, θja = 30° C/W
0.941" ± 0.010" 0.742" ±0.005"
80 81 51 50
T View op
0.11" nom.
Pin 1 Identifier 100 1 30 31
0.487" ±0.003"
0.705" ± 0.010"
0.009" ± 0.005" 0.031" ± 0.005"
Detail of pins
0.0256" ±0.002" 0.014" ± 0.002" 0.122" max.
Notes:
(1) (2) (3) (4)
Tolerances on pin spacing are not cumulative Dimensions shown are at seating plane I.C. denotes Internal Connection. This pin must be left unconnected. Do not use for vias. N.C. denotes No Connection. These pins can be used for vias.
PIN CONNECTIONS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD N.C. N.C. G10 G11 G12 G20 G21 G22 N.C. OBIN N.C. VSS SYMCKIN N.C. VSS DCLKIN N.C. VSS RESET 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS N.C. PNCG1 PNCG2 DSCRAM SYNC LDG2 N.C. N.C. VDD VDD COUNT0 COUNT1 COUNT2 COUNT3 COUNT4 COUNT5 COUNT6 COUNT7 VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS VDD PARL READ VSS ADDR2 ADDR1 ADDR0 WRITE CSEL VDD VDD N.C. DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DATA0 N.C. INT N.C. VSS ODCLK N.C. VSS DATO N.C. OOS AUTO N.C. I.C. N.C. BERR G1ERR G2ERR VDD VDD 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 THR0 THR1 THR2 THR3 THR4 THR5 THR6 THR7 EXTSEL VSS VSS VSS VDD VSS DDIF VSS RATE2 RATE1 RATE0 VDD
3
STEL-2060C
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INPUT SIGNALS
RESET
Reset. A logic low on this asynchronous input will completely reset all registers in the decoder to an initial condition within 20 nsec. Normal operation will commence after RESET goes high. This will not affect the values stored in the decision path memory but will reset the node sync state to the initial condition. inputs are accepted sequentially, using the G12-0 pins for both symbols. The sequential input is most suited for BPSK data, and the parallel input is most suited for QPSK data. The auto node sync sequence will operate on the assumption that the signal is BPSK modulated when PARL is set low and QPSK modulated when it is set high. Setting PARL low adds two cycles of ODCLK to the pipeline delay.
DCLKIN
Decoder clock input. It is the reference clock for all internal synchronous functions in the decoder when operating in the Internal Puncturing mode. It should nominally be a square wave with a maximum frequency of 45 MHz, corresponding to a decoded data rate of 45 Mbps. When operating at Rate 1 /2 and in the External Puncturing mode this clock will be generated internally from SYMCKIN, and DCLKIN should be connected to ground.
OBIN
The STEL-2060CCC can accept the soft-decision input data in either offset binary or offset signed-magnitude formats. When the OBIN input is set high, the format expected will be offset binary; when it is set low it will be offset signedmagnitude. The meanings of the 3-bit values for these two codes is shown in the following table: OBIN = 1 111 110 101 100 011 010 001 000 OBIN = 0 111 110 101 100 000 001 010 011 Value Most confident + (Data = 1) Least confident + Least confident – (Data = 0) Most confident –
SYMCKIN
Symbol clock input. This is the reference clock for all internal synchronous functions in the symbol alignment and depuncturing circuits. It should nominally be a square wave with a maximum frequency of 90 MHz. Its frequency should be equal to f DCLKIN/2R in the parallel input mode (PARL = 1) and equal to fDCLKIN/R in the sequential input mode (PARL = 0), where R is the decoding rate when using internal depuncturing. Please refer to the section on Punctured Mode Operation for more detailed information.
G12-0, G22-0
The G12-0 and G22-0 signals are the 3-bit soft decision input symbols to the decoder. They are presented to the decoder either sequentially or in parallel depending on the states of the PARL and RATE2-0 inputs. In the parallel mode (PARL = 1) the symbols are clocked into the device on the rising edges of SYMCKIN when RATE2-0 = 0 (Rate 1/2 and External Depuncturing) and on both edges of SYMCKIN when RATE2-0 ≠ 0 (Internal Depuncturing). In the sequential mode (PARL = 0) in which the 2-0 inputs are not used, both G2 the G1 and G2 symbols are loaded via the G12-0 pins. The G1 symbols are then latched in on the rising edges of SYMCKIN when LDG2 is low and the G2 symbols are latched in on the rising edges of SYMCKIN when LDG2 is high.
When using the STEL-2060CCC with hard-decision data, the symbols should be loaded into the G12 and G22 pins. The other symbol inputs should be set to a logic high level and OBIN should be set low.
RATE2-0
These signals select the decoding rate for unpunctured operation (Rate 1/2) and internally supported depuncturing patterns (Rates 2/3, 3/4 and 7/8). These patterns are shown in the following table, where a 0 in the pattern indicates a punctured symbol: RATE2-0 0 0 0 0 0 1 Rate
1 2
Pattern N.A. G1: 10 G2: 11 G1: 101 G2: 110 G1: 1000101 G2: 1111010
/2 /3
LDG2
When this signal is high during a rising edge of SYMCKIN the symbol loaded into the G12-0 pins will be G2. This function is only active when PARL is set low (sequential input mode) and RATE2-0 is set to 000 (Rate 1/2 operation or External Puncturing mode). If auto node sync is used, the LDG2 signal can be derived by dividing the SYMCKIN signal by two. The auto node sync will then compensate for the phase ambiguity. 1 0 0
3
/4
0 1 0
7
/8
Other puncturing patterns can be implemented externally using the PNCG1 and PNCG2 inputs.
PARL
When this signal is high, the input symbols are accepted in parallel by the chip, using the G12-0 pins for the G1 symbols and the G22-0 pins for the G2 symbols. When it is set low, the
DDIF
When this input is set high, it causes the data out of the Viterbi decoder to be differentially decoded. This adds one cycle of ODCLK to the pipeline delay.
STEL-2060C
4
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OUTPUT SIGNALS
DSCRAM
When this input is set high, it causes the G2 symbols to be inverted before they enter the Viterbi decoder, thereby reversing the effect of the G2 inversion if an "Invert G2" scrambler is implemented at the encoder.
ODCLK
Output data clock. All outputs change on the rising edge of this clock. The falling edge of ODCLK can be used as a strobe for DATO output, which is guaranteed to be valid on this edge.
PNCG1, PNCG2
The PNCG1 and PNCG2 signals are used to control the STEL-2060CCC when operating in punctured modes not supported by the internal puncturing logic. In normal operation (Rate 1/2 and when using internal puncturing) these pins should be set low. In the external depuncturing mode, the PNCG1 signal must be set high to indicate that the G1 symbol is punctured and the PNCG2 signal must be set high to indicate that the G2 symbol is punctured. A symbol will be depunctured when the PNCG1 or PNCG2 signals are high during the rising edge of SYMCKIN which latches the corresponding symbol in to the decoder. RATE2-0 should be set to 000 when operating in external depuncturing mode. Zero value metrics will be substituted internally for the actual metrics corresponding to the signals present on the G12-0 and G22-0 pins at that time. Internal depuncturing can be select
