N-CHANNEL MOSFET

www.DataSheet4U.com STD55NH2LL STD55NH2LL-1 N-channel 24V - 0.010Ω - 40A - DPAK/IPAK Ultra low gate charge STripFET™ Power MOSFET General features Type STD55NH2LL-1 STD55NH2LL VDSS 24V 24V RDS(on) <0.011Ω <0.011Ω ID 40A(1) 40A(1) 2 1 3 1 3 1. Value limited by wire bonding ■ ■ ■ ■ RDS(ON) * Qg industry’s benchmark Conduction losses reduced Switching losses reduced Low threshold device iPAK DPAK Description The STD55NH2LL is based on the latest generation of ST's proprietary STripFET™ technology. An innovative layout enables the device to also exhibit extremely low gate charge for the most demanding requirements as highside switch in high-frequency DC-DC converters. It's therefore ideal for high-density converters in Telecom and Computer applications. Internal schematic diagram Applications ■ Switching application Order codes Part number STD55NH2LL-1 STD55NH2LLT4 Marking D55NH2LL D55NH2LL Package IPAK DPAK Packaging Tube Tape & reel July 2006 Rev 5 1/16 www.st.com 16 Contents STD55NH2LL - STD55NH2LL-1 Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 4 5 6 7 Test circuit ................................................ 8 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 STD55NH2LL - STD55NH2LL-1 Electrical ratings 1 Electrical ratings Table 1. Symbol Vspike (1) VDS VDGR VGS ID(2) ID(2) IDM (3) Absolute maximum ratings Parameter Drain-source voltage rating Drain-source voltage (VGS = 0) Drain-gate voltage (RGS = 20 kΩ) Gate- source voltage Drain current (continuous) at TC = 25°C Drain current (continuous) at TC = 100°C Drain current (pulsed) Total dissipation at TC = 25°C Derating Factor Value 30 24 24 ± 16 40 28 160 60 0.4 600 -55 to 175 Max. operating junction temperature Unit V V V V A A A W W/°C mJ °C Ptot (4) EAS Single pulse avalanche energy Storage temperature Tstg Tj 1. Garanted when external Rg=4.7 Ω and tf < tfmax. 2. Value limited by wire bonding 3. Pulse width limited by safe operating area. 4. Starting Tj = 25 °C, ID = 20A, VDD = 15V Table 2. Rthj-case Rthj-amb TJ Thermal data Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose 2.5 100 275 °C/W °C/W °C 3/16 Electrical characteristics STD55NH2LL - STD55NH2LL-1 2 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 25mA, VGS =0 VDS = max rating VDS = max rating TC = 125°C VGS = ± 16V VDS = VGS, ID = 250µA VGS = 10V, ID = 20A VGS = 4.5V, ID = 20A 1 0.010 0.012 0.011 0.0135 Min. 24 1 10 ±100 Typ. Max. Unit V µA µA nA V Ω Ω IDSS IGSS VGS(th) RDS(on) Table 4. Symbol gfs (1) Ciss Coss Crss Dynamic Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Test conditions VDS = 10V, ID = 10A Min. Typ. 18 990 385 40 Max. Unit S pF pF pF VDS = 25V, f = 1MHz, VGS = 0 f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain VDD = 10V, ID = 20A RG = 4.7Ω VGS = 4.5V (see Figure 13) 0.44V ≤VDD ≤10V, ID = 40A, VGS = 4.5V, RG = 4.7Ω (see Figure 14) VDS= 16 V, VGS= 0 V RG Gate Input Resistance 1.3 Ω td(on) tr td(off) tf Qg Qgs Qgd Qoss(2) Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Output charge 15 56 13 10 8.7 4.2 2.4 7.6 11 ns ns ns ns nC nC nC nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Chapter 4: Appendix A 4/16 STD55NH2LL - STD55NH2LL-1 Electrical characteristics Table 5. Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 20A, VGS = 0 32.5 28 1.7 Test conditions Min. Typ. Max. 40 160 1.3 Unit A A V ns nC A Reverse recovery time ISD = 40A, di/dt = 100A/µs, Reverse recovery charge VDD = 15V, Tj = 150°C Reverse recovery current (see Figure 15) 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 5/16 Electrical characteristics STD55NH2LL - STD55NH2LL-1 2.1 Figure 1. Electrical characteristics (curves) Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/16 STD55NH2LL - STD55NH2LL-1 Figure 7. Gate charge vs gate-source voltage Figure 8. Electrical characteristics Capacitance variations Figure 9. Normalized gate threshold voltage vs temperature Figure 10. Normalized on resistance vs temperature Figure 11. Source-drain diode forward characteristics Figure 12. Normalized breakdown voltage vs temperature 7/16 Test circuit STD55NH2LL - STD55NH2LL-1 3 Test circuit Figure 14. Gate charge test circuit Figure 13. Switching times test circuit for resistive load Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform 8/16 STD55NH2LL - STD55NH2LL-1 Appendix A 4 Appendix A Figure 19. Buck converter: power losses estimation The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. ● ● ● ● ● ● ● ● ● ● ● The low side (SW2) device requires: Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires: Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses Low RDS(on) to reduce the conduction losses. 9/16 Appendix A STD55NH2LL - STD55NH2LL-1 Table 6. Power losses calculation High side switching (SW1) Low side switch (SW2) Pconduction R DS(on)SW1 * I 2 * δ L R DS(on)SW2 * I 2 * (1 − δ ) L IL Ig Pswitching Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * Zero Voltage Switching Recovery (1) Not applicable Vin * Q rr(SW2) * f Pdiode Conductio n Not applicable Vf(SW2) * I L * t deadtime * f Q gls(SW2) * Vgg * f Vin * Q oss(SW2) * f 2 Pgate(QG) Q g(SW1) * Vgg * f PQoss Vin * Q oss(SW1) * f 2 1. Dissipated by SW1 during turn-on Table 7. Paramiters meaning Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss 10/16 STD55NH2LL - STD55NH2LL-1 Package mechanical data 5 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/16 Package mechanical data STD55NH2LL - STD55NH2LL-1 TO-251 (IPAK) MECHANICAL DATA DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033 H C A C2 L2 D B3 B6 A1 L = = 3 B5 B A3 = B2 = G = E L1 1 2 = 0068771-E 12/16 STD55NH2LL - STD55NH2LL-1 Package mechanical data DPAK MECHANICAL DATA mm. DIM. MIN. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 5.1 6.4 4.7 2.28 4.4 9.35 1 2.8 0.8 0.6 0.2 0° 8° 0° 1 0.023 0.008 8° 4.6 10.1 0.173 0.368 0.039 0.110 0.031 0.039 6.6 0.252 0.185 0.090 0.181 0.397 TYP MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.200 0.260 TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 inch 0068772-F 13/16 Packing mechanical data STD55NH2LL - STD55NH2LL-1 6 Packing mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK