N-CHANNEL POWER MOSFET

www.DataSheet4U.com STD100NH02L STD100NH02L-1 N-channel 24V - 0.0042Ω - 60A - DPAK - IPAK STripFET™ II Power MOSFET General features Type STD100NH02L STD100NH02L-1 1. ■ ■ ■ ■ VDSSS 24V 24V RDS(on) <0.0048Ω <0.0048Ω ID 60A(1) 60A(1) 1 3 2 1 3 Value limited by wire bonding RDS(on) * Qg industry’s benchmark Conduction losses reduced Switching losses reduced Low threshold device DPAK IPAK Description This device utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable fot the most demanding DC-DC converter application where high efficiency is to be achieved. Internal schematic diagram Applications ■ Switching application Order codes Part number STD100NH02LT4 STD100NH02L-1 Marking D100NH02L D100NH02L Package DPAK IPAK Packaging Tape & reel Tube December 2006 Rev 11 1/16 www.st.com 16 Contents STD100NH02L Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 4 5 6 Test circuit ................................................ 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 STD100NH02L Electrical ratings 1 Electrical ratings Table 1. Symbol Absolute maximum ratings Parameter Value 30 24 24 ± 20 60 60 240 100 0.67 800 -55 to 175 Max. operating junction temperature Unit V V V V A A A W W/°C mJ °C Vspike (1) Drain-source voltage rating VDS VDGR VGS ID ID (2) (2) (3) Drain-source voltage (VGS = 0) Drain-gate voltage (RGS = 20KΩ) Drain-source voltage Drain current (continuous) at TC = 25°C Drain current (continuous) at TC=100°C Drain current (pulsed) Total dissipation at TC = 25°C Derating factor IDM PTOT (4) EAS Single pulse avalanche energy Storage temperature Tstg TJ 2. 1. Garanted when external Rg = 4.7 Ω and tf < tfmax. Value limited by wire bonding. 3. Pulse width limited by safe operating area 4. Starting TJ = 25 oC, ID = 30A, VDD = 15V Table 2. Symbol RthJC RthJA Tl Thermal data Parameter Thermal resistance junction-case Max Thermal resistance junction-ambient Max Maximum lead temperature for soldering purpose Value 1.5 100 275 Unit °C/W °C/W °C 3/16 Electrical characteristics STD100NH02L 2 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On/off states Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 25mA, VGS = 0 VDS = 20 VDS = 20, TC = 125°C VGS = ±20V VDS= VGS, ID = 250µA VGS = 10V, ID = 30A VGS = 5V, ID = 15A 1 1.8 0.0042 0.0048 0.005 0.009 Min. 24 1 10 ±100 Typ. Max. Unit V µA µA nA V Ω Ω Table 4. Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd Qoss(2) Qgls(3) RG Dynamic Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Output charge Third-quadrant gate charge Gate input resistance Test conditions VDS = 10 V, ID = 30A VDS = 15V, f = 1 MHz, VGS = 0 Min. Typ. 50 3940 1020 110 62 12 8 24 56.5 1.1 84 Max. Unit S pF pF pF nC nC nC nC nC Ω VDD = 10V, ID = 30A VGS = 10V VDS = 16V, VGS = 0V VDS < 0V, VGS = 10V f = 1MHz gate DC Bias = 0 Test signal level = 20mV Open drain 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 2. Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Chapter Appendix A 3. Gate charge for synchronous operation 4/16 STD100NH02L Electrical characteristics Table 5. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 10V, ID = 30A, RG = 4.7Ω, VGS = 10V Figure 13 on page 8 Min. Typ. 15 200 60 35 Max. Unit ns ns ns ns 47 Table 6. Symbol ISD ISDM VSD(1) trr Qrr IRRM Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 30A, VGS = 0 ISD = 60A, di/dt = 100A/µs, VDD = 15V, TJ = 150°C Figure 15 on page 8 47 58 2.5 Test conditions Min Typ. Max 60 240 1.3 Unit A A V ns µC A 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/16 Electrical characteristics STD100NH02L 2.1 Figure 1. Electrical characteristics (curves) Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/16 STD100NH02L Figure 7. Gate charge vs gate-source voltage Figure 8. Electrical characteristics Capacitance variations Figure 9. Normalized gate threshold voltage vs temperature Figure 10. Normalized on resistance vs temperature Figure 11. Source-drain diode forward characteristics Figure 12. Normalized breakdown voltage vs temperature 7/16 Test circuit STD100NH02L 3 Test circuit Figure 14. Gate charge test circuit Figure 13. Switching times test circuit for resistive load Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/16 STD100NH02L Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/16 Package mechanical data STD100NH02L TO-251 (IPAK) MECHANICAL DATA DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033 H C A C2 L2 D B3 B6 A1 L = = 3 B5 B A3 = B2 = G = E L1 1 2 = 0068771-E 10/16 STD100NH02L Package mechanical data DPAK MECHANICAL DATA mm. DIM. MIN. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 5.1 6.4 4.7 2.28 4.4 9.35 1 2.8 0.8 0.6 0.2 0° 8° 0° 1 0.023 0.008 8° 4.6 10.1 0.173 0.368 0.039 0.110 0.031 0.039 6.6 0.252 0.185 0.090 0.181 0.397 TYP MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.200 0.260 TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 inch 0068772-F 11/16 Packaging mechanical data STD100NH02L 5 Packaging mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 2500 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R W BASE QTY 2500 mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40 15.7 16.3 inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574 0.618 0.641 MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1 12/16 STD100NH02L Buck converter - power losses estimation Appendix A Buck converter - power losses estimation Figure 18. Buck converter: power losses estimation The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. ● ● ● ● ● ● ● ● ● ● ● The low side (SW2) device requires: Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires: Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses Low RDS(on) to reduce the conduction losses. 13/16 Buck converter - power losses estimation STD100NH02L Table 7. Power losses calculation High side switching (SW1) Low side switch (SW2) Pconduction R DS(on)SW1 * I 2 * δ L R DS(on)SW2 * I 2 * (1 − δ ) L IL Ig Pswitching Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * Zero Voltage Switching Recovery (1) Not applicable Vin * Q rr(SW2) * f Pdiode Conductio n Not applicable Vf(SW2) * I L * t deadtime * f Q gls(SW2) * Vgg * f Vin * Q oss(SW2) * f 2 Pgate(QG) Q g(SW1) * Vgg * f PQoss Vin * Q oss(SW1) * f 2 1. Dissipated by SW1 during turn-on Table 8. Paramiters meaning Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive los