PROGRAMMING MANUAL

www.DataSheet4U.com ST486DX SMM PROGRAMMING MANUAL 1st EDITION NOVEMBER 1994 GENERAL INDEX 1. SMM OVERVIEW Pages 9 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 SGS Thomson SMM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 A Typical SMM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SGS THOMSON SMM IMPLEMENTATION 13 2.1 Hardware Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 SMM Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 24 28 31 32 33 34 35 37 38 2. 3. SMM SOFTWARE CONSIDERATIONS 3.1 Enabling SMM . . . . . . . . . . . . . . . . . . . . . . 3.2 SMM Handler Entry State . . . . . . . . . . . . . . . . 3.3 Maintaining the CPU State . . . . . . . . . . . . . . . . 3.4 Initializing the SMM Environment . . . . . . . . . . . . 3.5 Accessing Main Memory Overlapped by SMM Memory 3.6 I/O Restart . . . . . . . . . . . . . . . . . . . . . . . . 3.7 I/O Port Shadowing and Emulation . . . . . . . . . . . 3.8 Return to HLT Instruction . . . . . . . . . . . . . . . . 3.9 Exiting the SMI Handler . . . . . . . . . . . . . . . . . 3.10 Testing and Debugging SMM Code . . . . . . . . . . . 4. POWER MANAGEMENT FEATURES 41 4.1 Reducing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 Lowering the CPU Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Assembler Macros for SGS Thomson Instructions 45 Appendix A 5 ST486DX - SMM OVERVIEW 1. 1.1 SMM OVERVIEW Introduction This Programmer’s Guide has been written to aid programmers in the creation of software using the SGS-Thomson System Management Mode (SMM) for ST486DX CPUs. This guide should be used in conjunction with the SGS-Thomson ST486DX and ST486DX2 Processors Data Book. SMM programming related to the ST486SLC/e is covered in the ST486SLC/e SMM Programmer’s Guide. SMM provides the system designer with another processor operating mode. Within this document the standard x86 operating modes (real, v86 and protected) are referred to as normal mode. Normal mode operation can be interrupted by an SMI interrupt or special instruction that places the processor in System Management Mode (SMM). SMM can be used to enhance the functionality of the system by providing power management, register shadowing, peripheral emulation and other system level functions. SMM can be totally transparent to all application software, including protected mode operating systems. 1.2 SGS-Thomson SMM Features SMM operation within one of the SGS-Thomson ST486DX microprocessors is similar to related operations performed by other x86 microprocessors. All processors with SMM capability, switch into real mode upon entry into the SMM interrupt handler. Each CPU has a unique SMM code locations. However, the SMM memory region for the SGS-Thomson CPU has a programmable location and size. All devices save some of the CPU registers upon entry to SMM. The SGS-Thomson CPU automatically saves minimal register information reducing the entry and exit clock count to as low as 100 clock cycles. This compares with Intel’s clock overhead for a typical entry and exit of 633 clock cycles. The SGS-Thomson SMM implementation provides unique instructions that save additional segment registers as required by the programmer. The x86 MOV instruction can be used to save the general purpose registers. Although all SMM capable CPUs provide I/O trapping, the SGS-Thomson CPUs simplify I/O type identification and instruction restarting. SGS-Thomson CPUs also make available to the SMM routine information which can simplify peripheral register shadowing. SGS-Thomson provides a method to prevent SMM configuration registers from being accessed by applications. Access to the SMM configuration can be prevented by setting a bit in the CPU configuration space. Not allowing an application to disable or alter SMM operation is useful for antivirus or security measures. 9 ST486DX - SMM OVERVIEW 1.3 Typical SMM Routines A typical SMM routine is illustrated in the flowchart shown in Figure 1-1. Upon entry to SMM, the CPU registers that will be used by the SMM routine, must be saved. The SMM environment is initialized by setting up an Interrupt Descriptor Table, initializing segment limits and setting up a stack. If the SMI was a result of an I/O bus cycle, the SMM routine can monitor peripheral activity, shadow read-only ports ,and/or emulate peripherals in software. If a peripheral was powered down, the SMM routine can power up a peripheral and reissue the I/O instruction. If the SMI was not caused by an I/O bus cycle, non-trap SMI functions can be serviced. If the instruction executing, when an SMI occurred, was a HLT instruction, the HLT instruction it should be restarted when the SMM routine is complete. Before normal operation is resumed, any CPU registers modified during the SMM routine must be restored to their previous state. SMM Entry Save State Initialize SMM Environment Service Non-Trap SMI N I/O Trap? Y Device OFF? N Y Service Trap SMI HALT? Y Decrement EIP Shadow or Emulate Modify State For I/O Restart N Restore State Resume 1727400 SMM Exit Figure 1 - 1. Typical SMM Routine 10 ST486DX - SMM IMPLEMENTATION 2. 2.1 2.1.1 SGS-Thomson SMM IMPLEMENTATION Hardware Background SMM Pins The signals at the SMI# and SMADS# pins are used to implement SMM. The SMI# pin is bi-directional. The SMI# pin is used by the chipset to signal the CPU that an SMI has occurred. While the CPU is in the process of servicing an SMI interrupt, the SMI# pin is an output used to signal the chipset that the SMM processing is occurring. The SMADS# address strobe signal is generated instead of an ADS# address strobe signal while executing or accessing data in SMM address space. 2.1.2 SMI# Pin Timing To enter SMM mode, the SMI# signal must be asserted for at least one CLK period (Two clocks if SMI# is asserted asynchronously). To accomplish I/O trapping, the SMI# signal should be asserted two clocks before the RDY# for that I/O cycle. Once the CPU recognizes the active SMI# input, the CPU drives the SMI input low for the duration of the SMI routine. The SMI routine is terminated with an SMI specific resume instruction (RSM). When the RSM instruction is executed, the CPU drives the SMI pin high for one CLK period. The SMI# pin must be allowed to go high for one CLK at the end of the SMI routine in order for the next SMI to be recognized. Since the SMI# pin is bi-directional, not more than one SMI# interrupt can become active at one time. 2.1.3 Address Strobes The CPU has two address strobes, ADS# and SMADS#. ADS# is the address strobe used during normal operations. The SMADS# address strobe replaces ADS# during SMM for memory accesses when data is written, read, or fetched in the SMM defined region. Using a separate address strobe increases chipset compatibility and control. During an SMM interrupt routine, control can be transferred to main memory via a JMP, CALL, Jcc instruction, execution of a software interrupt (INT), or a hardware interrupt (INTR or NMI). Execution in main memory will cause ADS# to be generated for code and data outside of the defined SMM address region. (It is assumed, but not required, that the chipset ultimately translates SMADS# and a particular address to some other address.) To access data in main memory that overlaps the SMM address space, the MMAC bit (CCR1, bit 3) must be set. This allows ADS# strobes to be generated for data accesses in memory which overlap SMM memory while in SMM mode. It is not possible to execute code in main memory that overlaps SMM space while in SMM mode. 13 ST486DX - SMM IMPLEMENTATION SMADS# can also be generated for memory reads/writes and code fetches within the defined SMM region when the SMAC bit (CCR1, bit 2) is set while in normal mode. The generation of SMADS# permits a program in normal mode to jump into SMM code space. The RSM instruction should not be executed after jumping into SMM space unless valid return information is first written into the SMM header. 2.1.4 Chipset RDY# The SGS Thomson CPU has one RDY# input. Chipsets that implement the dual ready lines (one for SMM and one for normal memory) can logically OR the two ready lines together to produce a single RDY# line. 2.1.5 Cache Coherency SMM memory is never cached in the CPU internal cache. This makes cache coherency completely transparent to the SMM programmer. If the CPU cache is in write-back mode, all write-back cycles will be directed to normal memory with the use of the ADS# signal. An INVD or WBINVD will write dirty data out to normal memory even if it overlaps with SMM space. SMM memory can be cached by a external cache controller, but it is up to the cache designer to be sure to maintain a distinction between SMM memory space and normal memory space. The A20M# input to the CPU is ignored for all SMM space accesses (any accesses which uses SMADS#). 2.2 Configuration Control Registers This section describes how to use the Configuration Control Registers in SMM code. For a complete description of th