ST 486 DX ASIC CORE

www.DataSheet4U.com ST 486 DX ASIC CORE Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE PRELIMINARY DATA s s s s s s s s s s Fully Static 486 compatible core able to operate from D.C to 120MHz Manufactured in a 0.35 micron five layer metal HCMOS process 8K byte unified instruction and data cache with write back capability Parallel processing integral floating point unit, with automatic power down mode Low Power system management modes Cell libraries for 2.2V and 3.3V supply with 5 V I/O interface capability 2 - input NAND delay of 0.160 ns (typ) with fanout = 2. Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS. High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike suppression and impedance matching. Generators to support SPRAM, DPRAM, ROM and many other embedded functions. s s s s s s s s s s s Fully independent power and ground configurations for inputs, core and outputs. Programmable I/O ring capability up to 1000 pads. Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels. Active pull up and pull down devices. Buskeeper I/O functions. Oscillators for wide frequency spectrum. Broad range of 400 SSI cells. Design For Test includes LSSD macro library option and IEEE 1149.1 JTAG Boundary Scan architecture built in. Cadence based design system with interfaces from multiple workstations. Broad ceramic and plastic package range. Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts. Figure 1. Example 486 DX Core ASIC S e a o f G at e s S t a n d ar d C e l ls A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAA AAAA AA AA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAA AAAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAA AA AAAAAA AAAAAAAAAAAAAA AAAAAAAA A AA AAAAAA AAAA AAAA AAAAA AAAAAA AAAA AAAA AAAAA AAAAAAAAAA AAAA AAAAAAAA AAAA AA AAAA AAAA AAAAAA AAAA AAAA AAAA AAAA AAAA AAAA SV G A C H IP S E T / P C I ID E / IS A 486 AAAAAA AAAAAA AAAAAA ROM AAAAAA AAA AAAAAA AAAAAA RAM AAAAAA AAA AAAAAA D P R A M AAAAAA AAA AAAAAA AAAAAA AAAA AAAAAA AAA AAAAA AAAA AAAAAA AAA AAAAA AAAAAA AAA AAAAAAAA AA AAA AAAA AAAAAAAA AAAAA AAAAA AAAAAA AAAAAA AA AAAAAA AAAAAAAA AAAAAA AAAAAA A AAAA AAAAA AAAA AAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAA AAAA AAAAAAA AAAA AAAA AAAA DX CORE AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAA AAAA C u s t o m I/ O e .g R A M D A C October 1995 P r o g ra m m a b le I/O 1/8 ST 486 DX ASIC CORE PRODUCT OVERVIEW The ST 486 DX core is based on the design of the SGS-THOMSON standard 486 DX4 product. The core is capable of operating at the “external” bus speed or at two or three times the bus speed up to a maximum of 120MHz. Since the design is fully static the core can operate at any frequency between D.C and 120MHz. The core is manufactured on a high performance, low voltage, five level metal, HCMOS 0.35 micron process to achieve sub-nanosecond internal speeds while offering very low power dissipation and high noise immunity. The potential total gate count for application specific devices exceeds 2 million equivalent usable gates. The core operates over a Vdd voltage range of 2.2 to 3.6 volts. The core comes available with a full range of SSI, MSI libraries as well as generators for SPRAM, DPRAM, ROM. Where process and design philosophy permit it is possible to integrate existing “standard DEVICES” within a 486 core design. A full set of “chipset” function blocks are available to build support subsystems on chip blocks such as IDE controller, PCI bridge, DRAM controller etc. The I/O can be configured for circuits ranging from low voltage CMOS and TTL to 200 MHz plus low swing differential circuits. CLOCK-TRIPLED CPU CORE The ST486DX Core in DX4 mode provides up to 2.8 times the performance of a 486DX at the same “external” clock frequency. This level of performance is achieved by tripling the frequency of the input clock and using the resulting signal to drive the CPU core. To further enhance this architecture, the ST486DX Core reduces the performance penalty of slow external memory accesses through use of an on-chip write-back cache and eight write buffers. The CPU core consists of a five-stage pipeline optimized for minimal instruction cycle times and includes all necessary hardware interlocks to permit successive instruction execution overlap. The execution stage of the pipeline executes simple but frequently used instructions in a single clock cycle and the hardware multiplier executes 16-bit integer multiplications in only three clocks. ON-CHIP WRITE-BACK CACHE The ST486DX Core on-chip cache can be configured to run in traditional write-through mode or in a higher performance write-back mode. The write-back cache mode was specifically designed to optimize performance of the CPU core by eliminating bus bottlenecks caused by unnecessary external write cycles. This writeback architecture is especially effective in improving performance of the clock-tripled ST486DX4 Core. Traditional write-through cache architecture require that all writes to the cache also update external memory simultaneously. These unnecessary write cycles create bottlenecks which result in CPU stalls and adversely impact performance. In contrast, a write-back architecture allows data to be written to the cache without updating external memory. With a writeback cache, external write cycles are only required when a cache miss occurs, a modified line is replaced in the cache, or when an external bus master requires access to data. The ST486DX Core cache is an 8-Kilobyte unified instruction and data cache implemented using a four-way set associative architecture and a least recently used (LRU) replacement algorithm. The cache is designed for optimum performance in write-back mode, however, the cache can be operated in write-through mode. The cache line size is 16 bytes and new lines are only allocated during memory read cycles. Valid status is maintained on a 16-byte cache line basis, but modified or "dirty" status for write-back mode is maintained on a 4-byte (double-word) basis. Therefore, only the double-words that have been modified are written back to external memory when a line is replaced in the cache. The CPU core can access the cache in a single internal clock cycle for both reads and writes. FPU OPERATIONS Since the FPU is resident within the CPU, the overhead associated with external maths capriciousness cycles is eliminated. If the FPU is not in use, the FPU is automatically powered down. This feature reduces overall power consumption. 2/8 ® ST 486 DX ASIC CORE SYSTEM MANAGEMENT MODE System Management Mode (SMM) provides an additional interrupt and a separate address space that can be used for system power management or software transparent emulation of I/O peripherals. SMM is entered using the System Management Interrupt (SMI#) or SMINT instruction. While running in isolated SMM address space, the SMI interrupt routine can execute without interfering with the operating system or application programs. After entering SMM, portions of the CPU state are automatically saved. Program execution begins at the base of SMM address space. The location and size of the SMM memory are programmable within the ST486DX Core. Eight SMM instructions have been added to the 486 instruction set that permit software entry into SMM, as well as saving and restoring the total CPU state when in SMM mode. POWER MANAGEMENT The ST486DX Core power management features allow for a dramatic improvement in battery life over systems designed with non-static 486 processors. During suspend mode the typical current consumption is less than 1 percent of the full operation current. Suspend mode is entered by either a hardware or a software initiated action. Using the hardware method to initiate suspend mode involves a twopin handshake between the SUSP# and SUSPA# signals. The software can initiate suspend mode through the execution of the HALT instruction. Once in suspend mode, the ST486DX Core power consumption is further reduced by stopping the external clock input. The resulting current draw is typically 450 µA. Since the ST486DX Core is static, no internal data is lost when the clock is stopped. SIGNAL SUMMARY The ST486DX Core signal set includes ten cache interface signals, two capriciousness interface signals, two power management signals, two system management mode signals, one power supply voltage control signal and one clock multiplier control signal. LIBRARY The following section details the elements which make up the ST486DX core HCMOS6 library. The elements are organised into three categories: - Macrocell & Macrofunctions - Module generators - Embedded Functions MACROCELLS AND MACROFUNCTIONS The HCMOS 6 library has internal macrocells that are robust in variety and performance. The cell selecti