N-Channel MOSFET

www.DataSheet4U.com SSR4N60B / SSU4N60B November 2001 SSR4N60B / SSU4N60B 600V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supplies. Features • • • • • • 2.8A, 600V, RDS(on) = 2.5Ω @VGS = 10 V Low gate charge ( typical 22 nC) Low Crss ( typical 14 pF) Fast switching 100% avalanche tested Improved dv/dt capability D D ! ! # " ! ! G S D-PAK SSR Series I-PAK G D S SSU Series G! ! S Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) SSR4N60B / SSU4N60B 600 2.8 1.8 11.2 ± 30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) * Power Dissipation (TC = 25°C) 240 2.8 4.9 5.5 2.5 49 0.39 -55 to +150 300 TJ, Tstg TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8!"from case for 5 seconds Thermal Characteristics Symbol RθJC RθJA RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient * Thermal Resistance, Junction-to-Ambient Typ ---Max 2.56 50 110 Units °C/W °C/W °C/W * When mounted on the minimum pad size recommended (PCB Mount) ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSR4N60B / SSU4N60B Electrical Characteristics Symbol Parameter TC = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ∆BVDSS / ∆TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 600 V, VGS = 0 V VDS = 480 V, TC = 125°C VGS = 30 V, VDS = 0 V VGS = -30 V, VDS = 0 V 600 ------0.65 ------10 100 100 -100 V V/°C µA µA nA nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 µA VGS = 10 V, ID = 1.4 A VDS = 40 V, ID = 1.4 A (Note 4) 2.0 --- -2.0 3.7 4.0 2.5 -- V Ω S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---710 65 14 920 85 19 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 480 V, ID = 4.0 A, VGS = 10 V (Note 4, 5) VDD = 300 V, ID = 4.0 A, RG = 25 Ω (Note 4, 5) -------- 20 55 70 55 22 4.8 8.5 50 120 150 120 29 --- ns ns ns ns nC nC nC Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 2.8 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 4.0 A, dIF / dt = 100 A/µs (Note 4) ------ ---330 2.67 2.8 11.2 1.4 --- A A V ns µC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 56mH, IAS = 2.8A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD # 4.0A, di/dt # 300A/µs, VDD # BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width # 300µs, Duty cycle # 2% 5. Essentially independent of operating temperature ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSR4N60B / SSU4N60B Typical Characteristics 10 1 ID, Drain Current [A] 10 0 ID, Drain Current [A] VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V Bottom : 5.0 V Top : 10 1 150 C 10 0 o 25 C -55 C o o 10 -1 % Notes : 1. 250& s Pulse Test 2. TC = 25$ % Notes : 1. VDS = 40V 2. 250& s Pulse Test 10 -1 10 -1 10 0 10 1 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 12 10 1 10 RDS(ON) [' ], Drain-Source On-Resistance 8 6 VGS = 20V IDR, Reverse Drain Current [A] VGS = 10V 10 0 4 150$ 25$ % Notes : 1. VGS = 0V 2. 250& s Pulse Test 2 % Note : TJ = 25$ 0 0 2 4 6 8 10 12 10 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID, Drain Current [A] VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature 1500 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 10 VDS = 120V VDS = 300V 1000 VGS, Gate-Source Voltage [V] Capacitance [pF] Ciss 8 VDS = 480V 6 500 Coss Crss % Notes : 1. VGS = 0 V 2. f = 1 MHz 4 2 % Note : ID = 4.0 A 0 -1 10 0 10 0 10 1 0 4 8 12 16 20 24 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSR4N60B / SSU4N60B Typical Characteristics (Continued) 1.2 3.0 2.5 BV DSS , (Normalized) Drain-Source Breakdown Voltage RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 2.0 1.0 1.5 1.0 0.9 % Notes : 1. VGS = 0 V 2. ID = 250 & A 0.5 % Notes : 1. VGS = 10 V 2. ID = 2.0 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs Temperature Figure 8. On-Resistance Variation vs Temperature 3.0 Operation in This Area is Limited by R DS(on) 10 1 2.5 100 µs 10 µs ID, Drain Current [A] 1 ms 10 0 10 ms DC 10 -1 % Notes : 1. TC = 25 C o 2. TJ = 150 C 3. Single Pulse o 10 -2 ID, Drain Current [A] 2.0 1.5 1.0 0.5 10 0 10 1 10 2 10 3 0.0 25 50 75 100 125 150 VDS, Drain-Source Voltage [V] TC, Case Temperature [$] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs Case Temperature (t), T h e r m a l R e s p o n s e D = 0 .5 10 0 0 .2 0 .1 0 .0 5 10 -1 % N o te s : 1 . Z ( J C (t) = 2 .5 6 $ /W M a x . 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T C = P D M * Z ( J C (t) ( JC 0 .0 2 0 .0 1 s in g le p u ls e PDM t1 t2 Z 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSR4N60B / SSU4N60B Gate Charge Test Circuit & Waveform 50K) 12V 200nF 300nF Same Type as DUT VDS VGS Qg 10V Qgs Qgd VGS DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS VGS RG RL VDD VDS 90% 10V DUT VGS 10% td(on) t on tr td(off) t off tf Unclamped Inductive Switching Test Circuit & Waveforms L VDS ID RG DUT tp BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS VDD VDD tp ID (t) VDS (t) Time 10V ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSR4N60B / SSU4N60B Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG Same Type as DUT VDD VGS • dv/dt controlled by RG • ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 SSR4N60B / SSU4N60B Package Dimensions D-PAK 6.60 ±0.20 5.34 ±0.30 (0.50) (4.34) (0.50) 0.70 ±0.20 2.30 ±0.10 0.50 ±0.10 0.60 ±0.20 6.10 ±0.20 2.70 ±0.20 9.50 ±0.30 0.91 ±0.10 0.80 ±0.20 MAX0.96 2.30TYP [2.30±0.20] 0.76 ±0.10 2.30TYP [2.30±0.20] 0.89 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30 ±0.20 6.60 ±0.20 (5.34) (0.70) (0.90) (0.10) 0.76 ±0.10 Dimensions in Millimeters ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 MIN0.55 (3.05) (1.00) (5.04) (1.50) 6.10 ±0.20 9.50 ±0.30 2.70 ±0.20 (2XR0.25) SSR4N60B / SSU4N60B Package Dimensions (Continued) I-PAK 6.60 ±0.20 5.34 ±0.20 (0.50) (4.34) (0.50) 0.50 ±0.10 2.30 ±0.20 0.60 ±0.20 0.70 ±0.20 0.80 ±0.10 6.10 ±0.20 1.80 ±0.20 MAX0.96 0.76 ±0.10 9.30 ±0.30 2.30TYP [2.30±0.20] 2.30TYP [2.30±0.20] 0.50 ±0.10 Dimensions in Millimeters ©2001 Fairchild Semiconductor Corporation Rev. B, November 2001 16.10 ±0.30 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS™ EnSigna™ FACT™ FACT Quiet Series™ FAST® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER® SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TruTranslation™ TinyLogic™ UHC™ UltraFET® VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE O