16 Megabit (1M x 16-Bit) Multi-Purpose Flash

16 Megabit (1M x 16-Bit) Multi-Purpose Flash SST39VF160Q / SST39VF160 Advance Information FEATURES: • Organized as 1 M X 16 • Single 2.7V-only Read and Write Operations • VDDQ Power Supply to Support 5V I/O for SST39VF160Q - VDDQ not available on SST39VF160 • Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention • Low Power Consumption: - Active Current: 15 mA (typical) - Standby Current: 3 µA (typical) - Auto Low Power Mode: 3 µA (typical) • Small Sector Erase Capability (512 sectors) - Uniform 2 KWord sectors • Block Erase Capability (32 blocks) - Uniform 32 KWord blocks • Fast Read Access Time: - 70 and 90 ns PRODUCT DESCRIPTION The SST39VF160Q/VF160 devices are 1M x 16 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF160Q/VF160 write (Program or Erase) with a 2.7V-only power supply. The SST39VF160Q/VF160 conform to JEDEC standard pinouts for x16 memories. Featuring high performance word program, the SST39VF160Q/VF160 devices provide a maximum word-program time of 10 µsec. The entire memory can typically be erased and programmed word by word in 7 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, the SST39VF160Q/VF160 have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39VF160Q/VF160 are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39VF160Q/VF160 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST39VF160Q/VF160 significantly improve performance and reliability, while lowering power consumption. The SST39VF160Q/VF160 inherently use less energy during Ease and Program than • Latched Address and Data • Fast Sector Erase and Word Program: - Sector Erase Time: 3 ms typical - Block Erase Time: 7 ms typical - Chip Erase Time: 15 ms typical - Word Program time: 7 µs typical - Chip Rewrite Time: 7 seconds • Automatic Write Timing - Internal Vpp Generation • End of Write Detection - Toggle Bit - Data# Polling • CMOS I/O Compatibility • JEDEC Standard - EEPROM Pinouts and command set • Packages Available - 48-Pin TSOP (12mm x 20mm) - 6 x 8 Ball TFBGA alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST39VF160Q/ VF160 also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of endurance cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated endurance cycles. To meet high density, surface mount requirements, the SST39VF160Q/VF160 are offered in 48-pin TSOP and 48-pin TFBGA packages. See Figures 1 and 2 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc. 329-09 11/98 These specifications are subject to change without notice. 1 16 Megabit Multi-Purpose Flash SST39VF160Q / SST39VF160 Advance Information The SST39VF160Q/VF160 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. This reduces the IDD active read current from typically 15 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. Read The Read operation of the SST39VF160Q/VF160 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Word Program Operation The SST39VF160Q/VF160 are programmed on a wordby-word basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load word address and word data. During the word Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Sector/Block Erase Operation The Sector/Block Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST39VF160Q/VF160 offer both small Sector Erase and Block Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block Erase mode is based on uniform block size of 32 KWord. The Sector Erase operation is initiated by executing a six-bytecommand sequence with Sector Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A11-A19 are used to determine the sector address. The Block Erase operation is initiated by executing a six© 1998 Silicon Storage Technology, Inc. byte-command sequence with Block Erase command (50H) and block address (BA) in the last bus cycle. The address lines A15-A19 are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The end of Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 8 and 9 for timing waveforms. Any commands issued during the Sector or Block Erase operation are ignored. Chip-Erase Operation The SST39VF160Q/VF160 provide a Chip Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip Erase operation is initiated by executing a six byte command sequence with Chip Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the chip erase operation are ignored. Write Operation Status Detection The SST39VF160Q/VF160 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising edge of WE#, which initiates the internal program or erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST39VF160Q/VF160 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is 2 329-09 11/98 16 Megabit Multi-Purpose Flash SST39VF160Q / SST39VF160 Advance Information then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1�