(SST32HFxxx) Multi-Purpose Flash (MPF) + SRAM ComboMemory

www.DataSheet4U.com Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 SST32HF802 / 162 / 164MPF (x16) + 1Mb SRAM (x16) ComboMemories Data Sheet FEATURES: • MPF + SRAM ComboMemory – SST32HF802: 512K x16 Flash + 128K x16 SRAM – SST32HF162: 1M x16 Flash + 128K x16 SRAM – SST32HF164: 1M x16 Flash + 256K x16 SRAM • Single 2.7-3.3V Read and Write Operations • Concurrent Operation – Read from or write to SRAM while Erase/Program Flash • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 15 mA (typical) for Flash or SRAM Read – Standby Current: 20 µA (typical) • Flexible Erase Capability – Uniform 2 KWord sectors – Uniform 32 KWord size blocks • Fast Read Access Times: – Flash: 70 ns and 90 ns – SRAM: 70 ns and 90 ns • Latched Address and Data for Flash • Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Word-Program Time: 14 µs (typical) – Chip Rewrite Time: SST32HF802: 8 seconds (typical) SST32HF162/164: 15 seconds (typical) • Flash Automatic Erase and Program Timing – Internal VPP Generation • Flash End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Package Available – 48-lead TSOP (12mm x 20mm) – 48-ball TBGA (10mm x 12mm) PRODUCT DESCRIPTION The SST32HF802/162/164 ComboMemory devices integrate a 512K x16 or 1M x16 CMOS flash memory bank with a 128K x16 or 256K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high performance SuperFlash technology. Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 14 µsec. The entire flash memory bank can be erased and programmed word-by-word in typically 8 seconds for the SST32HF802 and 15 seconds for the SST32HF162/164, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST32HF802/ 162/164 devices contain on-chip hardware and software data protection schemes.The SST32HF802/162/164 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HF802/162/164 devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory ©2001 Silicon Storage Technology, Inc. S71171-05-000 8/01 520 1 bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST32HF802/162/164 provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled erase or program cycle in the flash bank has commenced, the SRAM bank can be accessed for read or write. The SST32HF802/162/164 devices are suited for applications that use both flash memory and SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF802/162/164 devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST32HF802/162/164 inherently use less energy during erase and program than alternative flash The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 Data Sheet technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. SRAM Write The SRAM Write operation of the SST32HF802/162/164 is controlled by WE# and BES# being low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of WE# or BES#, which ever occurs first. The write time is measured from the last falling edge to the rising edge of WE# or BES#. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. Flash Operation With BEF# active, the SST32HF162/164 operate as 1M x16 flash memory and the SST32HF802 operates as 512K x16 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and during the internally timed Erase and Program operations. Device Operation The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operation. When BEF# is low the flash bank is activated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by SRAM Bank and flash bank which minimizes power consumption and loading. The device goes into standby when both bank enables are high. Flash Read The Read operation of the SST32HF802/162/164 devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 6 for further details. SRAM Operation With BES# low and BEF# high, the SST32HF802/162 operate as 128K x16 CMOS SRAM, and the SST32HF164 operates as 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST32HF802/162 SRAM is mapped into the first 128 KWord address space of the device, and the SST32HF164 SRAM is mapped into the first 256 KWord address space. When BES# and BEF# are high, both memory banks are deselected and the device enters standby mode. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 3 for SRAM read and write data byte control modes of operation. Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST32HF802/162/ 164. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. SRAM Read The SRAM Read operation of the SST32HF802/162/164 is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 3 for the Read cycle timing diagram. ©2001 Silicon Storage Technology, Inc. Flash Word-Program Operation The flash memory bank of the SST32HF802/162/164 devices is programmed on a word-by-word basis. Before the Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses S71171-05-000 8/01 520 2 Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF802 / SST32HF162 / SST32HF164 Data Sheet are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bi