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www.DataSheet4U.com Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 SST32HF1621C / SST32HF1641C / SST32HF3241C SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM (x16) MCP ComboMemories Preliminary Specifications FEATURES: • ComboMemories organized as: – SST32HF1621C: 1M x16 Flash + 128K x16 SRAM – SST32HF1641x: 1M x16 Flash + 256K x16 SRAM – SST32HF1681: 1M x16 Flash + 256K x16 SRAM – SST32HF3241x: 2M x16 Flash + 256K x16 SRAM – SST32HF3281: 2M x16 Flash + 512K x16 SRAM • Single 2.7-3.3V Read and Write Operations • Concurrent Operation – Read from or Write to SRAM while Erase/Program Flash • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 15 mA (typical) for Flash or SRAM Read – Standby Current: - SST32HFx1: 60 µA (typical) - SST32HFx1C: 12 µA (typical) • Flexible Erase Capability – Uniform 2 KWord sectors – Uniform 32 KWord size blocks • Erase-Suspend/Erase-Resume Capabilities • Security-ID Feature – SST: 128 bits; User: 128 bits • Hardware Block-Protection/WP# Input Pin – Bottom Block-Protection (bottom 32 KWord) • Fast Read Access Times: – Flash: 70 ns – SRAM: 70 ns • Latched Address and Data for Flash • Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical) • Flash Automatic Erase and Program Timing – Internal VPP Generation • Flash End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Package Available – 63-ball LFBGA (8mm x 10mm x 1.4mm) – 62-ball LFBGA (8mm x 10mm x 1.4mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST32HFx1/x1C ComboMemory devices integrate a CMOS flash memory bank with a CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high performance SuperFlash technology. The SST32HF16x1/32x1 devices use a PseudoSRAM. The SST32HF16x1C/32x1C devices use standard SRAM. Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 µsec. To protect against inadvertent flash write, the SST32HFx1/x1C devices contain on-chip hardware and software data protection schemes. The SST32HFx1/x1C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HFx1/x1C devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable ©2005 Silicon Storage Technology, Inc. S71236-04-000 5/05 1 signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST32HFx1/x1C provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 SST32HF1621C / SST32HF1641C / SST32HF3241C Preliminary Specifications The SST32HFx1/x1C devices are suited for applications that use both flash memory and (P)SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HFx1/x1C devices significantly improve performance and reliability while lowering power consumption when compared with multiple chip solutions. The SST32HFx1/x1C inherently use less energy during Erase and Program operations than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since, for any given voltage range, SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. Concurrent Read/Write Operation The SST32HFx1/x1C provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from SRAM, while altering the data in flash. See Figure 26 for a flowchart. The following table lists all valid states. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Flash Read Operation The Read operation of the SST32HFx1/x1C devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 6 for further details. Device Operation The SST32HFx1/x1C use BES1#, BES2 and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the SRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low. ©2005 Silicon Storage Technology, Inc. S71236-04-000 5/05 2 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 SST32HF1621C / SST32HF1641C / SST32HF3241C Preliminary Specifications Flash Word-Program Operation The flash memory bank of the SST32HFx1/x1C devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs last. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 10 µs. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. During the command sequence, WP# should be statically held high or low. Any SDP commands loaded during the internal Program operation will be ignored. Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Flash Chip-Erase Operation The SST32HFx1/x1C provide a Chip-Erase

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SST32HF3281

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