(SST28xF040A) 4 Mbit (512K x8) SuperFlash EEPROM

4 Mbit (512K x8) SuperFlash EEPROM SST28SF040A / SST28VF040A SST28SF040A / SST28VF040A5.0 & 2.7 4Mb (x8) Byte-Program, Small Erase Sector flash memories Data Sheet FEATURES: • Single Voltage Read and Write Operations – 5.0V-only for SST28SF040A – 2.7-3.6V for SST28VF040A • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Memory Organization: 512K x8 • Sector-Erase Capability: 256 Bytes per Sector • Low Power Consumption – Active Current: 15 mA (typical) for 5.0V and 10 mA (typical) for 2.7-3.6V – Standby Current: 5 µA (typical) • Fast Sector-Erase/Byte-Program Operation – Byte-Program Time: 35 µs (typical) – Sector-Erase Time: 2 ms (typical) – Complete Memory Rewrite: 20 sec (typical) • Fast Read Access Time – 5.0V-only operation: 90 and 120 ns – 2.7-3.6V operation: 150 and 200 ns • Latched Address and Data • Hardware and Software Data Protection – 7-Read-Cycle-Sequence Software Data Protection • End-of-Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm and 8mm x 20mm) – 32-pin PDIP PRODUCT DESCRIPTION The SST28SF/VF040A are 512K x8 bit CMOS SectorErase, Byte-Program EEPROMs. The SST28SF/VF040A are manufactured using SST’s proprietary, high performance CMOS SuperFlash EEPROM Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternative approaches. The SST28SF/VF040A erase and program with a single power supply. The SST28SF/ VF040A conform to JEDEC standard pinouts for byte wide memories and are compatible with existing industry standard flash EEPROM pinouts. Featuring high performance programming, the SST28SF/ VF040A typically Byte-Program in 35 µs. The SST28SF/ VF040A typically Sector-Erase in 2 ms. Both Program and Erase times can be optimized using interface features such as Toggle bit or Data# Polling to indicate the completion of the Write cycle. To protect against an inadvertent write, the SST28SF/VF040A have on chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST28SF/ VF040A are offered with a guaranteed sector endurance of 10,000 cycles. Data retention is rated greater than 100 years. The SST28SF/VF040A are best suited for applications that require reprogrammable nonvolatile mass storage of program, configuration, or data memory. For all system appli©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310 1 cations, the SST28SF/VF040A significantly improve performance and reliability, while lowering power consumption when compared with floppy diskettes or EPROM approaches. Flash EEPROM technology makes possible convenient and economical updating of codes and control programs on-line. The SST28SF/VF040A improve flexibility, while lowering the cost of program and configuration storage application. The functional block diagram shows the functional blocks of the SST28SF/VF040A. Figures 1, 2, and 3 show the pin assignments for the 32-lead PLCC, 32-lead TSOP and 32, pin PDIP packages. Pin descriptions and operation modes are described in Tables 2 through 5. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Note, during the Software Data Protection sequence the addresses are latched on the rising edge of OE# or CE#, whichever occurs first. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Command Definitions Table 4 contains a command list and a brief summary of the commands. The following is a detailed description of the operations initiated by each command. command can be reissued as many times as necessary to complete the Chip-Erase operation. The SST28SF/ VF040A cannot be over-erased. (See Figure 8) Byte-Program Operation The Byte-Program operation is initiated by writing the setup command (10H). Once the program setup is performed, programming is executed by the next WE# pulse. See Figures 5 and 6 for timing waveforms. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first, and begins the Program operation. The Program operation is terminated automatically by an internal timer. See Figure 16 for the programming flowchart. The two-step sequence of a setup command followed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed. Sector-Erase Operation The Sector-Erase operation erases all bytes within a sector and is initiated by a setup command and an execute command. A sector contains 256 Bytes. This sector erasability enhances the flexibility and usefulness of the SST28SF/ VF040A, since most applications only need to change a small number of bytes or sectors, not the entire chip. The setup command is performed by writing 20H to the device. The execute command is performed by writing D0H to the device. The Erase operation begins with the rising edge of the WE# or CE#, whichever occurs first and terminates automatically by using an internal timer. The End-ofErase can be determined using either Data# Polling, Toggle Bit, or Successive Reads detection methods. See Figure 9 for timing waveforms. The two-step sequence of a setup command followed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. The Byte-Program Flowchart Description Programming data into the SST28SF/VF040A is accomplished by following the Byte-Program flowchart shown in Figure 16. The Byte-Program command sets up the byte for programming. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first and begins the Program operation. The end of program can be detected using either the Data# Polling, Toggle bit, or Successive reads. Sector-Erase Flowchart Description Fast and reliable erasing of the memory contents within a sector is accomplished by following the Sector-Erase flowchart as shown in Figure 18. The entire procedure consists of the execution of two commands. The Sector-Erase operation will terminate after a maximum of 4 ms. A Reset command can be executed to terminate the Sector-Erase operation; however, if the Erase operation is terminated prior to the 4 ms time-out, the sector may not be fully erased. A Sector-Erase command can be reissued as many times as necessary to complete the Erase operation. The SST28SF/VF040A cannot be over-erased. Reset Operation The Reset command is provided as a means to safely abort the Erase or Program command sequences. Following either setup commands (Erase or Program) with a write of FFH will safely abort the operation. Memory contents will not be altered. After the Reset command, the device returns to the Read mode. The Reset command does not enable Software Data Protection. See Figure 7 for timing waveforms. Chip-Erase Operation The Chip-Erase operation is initiated by a setup command (30H) and an execute command (30H). The Chip-Erase operation allows the entire array of the SST28SF/VF040A to be erased in one operation, as opposed to 2048 SectorErase operations. Using the Chip-Erase operation will minimize the time to rewrite the entire memory array. The ChipErase operation will terminate after a maximum of 20 ms. A Reset command can be executed to terminate the Erase operation; however, if the Chip-Erase operation is terminated prior to the 20 ms time-out, the chip may not be completely erased. If an erase error occurs a Chip-Erase ©2001 Silicon Storage Technology, Inc. Read The Read operation is initiated by setting CE#, and OE# to logic low and setting WE# to logic high (See Table 3). See Figure 4 for Read cycle timing waveform. The Read operation from the host retrieves data from the array. The device remains enabled for Read until another operation mode is accessed. During initial power-up, the device is in the Read mode and is Software Data protected. The device must be unprotected to execute a Write command. S71077-04-000 6/01 310 2 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet The Read operation of the SST28SF/VF040A are controlled by OE# and CE# at logic low. When CE # is high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when CE# or OE# are high. rising edge of OE# or CE#, whichever occurs first. A similar seven read sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the device. Also refer to Figures 10 and 11 for the 7 read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tri-state). Read-ID operation The Read-ID operation is initiated by writing a single command (90H). A read of address 0000H will output the manufacturer’s ID (BFH). A read of address 0001H will output the device ID (04H). Any other valid command will terminate this operation. Write Operation Status Detection The SST28SF/VF040A provide three means to detect the completion of a Write operation, in order to optimize the system Write operation. The end o