(SST25LF020A / SST25LF040A) 2 Mbit / 4 Mbit SPI Serial Flash

www.DataSheet4U.com 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A SST25LF020A / 040A2Mb / 4Mb Serial Peripheral Interface (SPI) flash memory Data Sheet FEATURES: • Single 3.0-3.6V Read and Write Operations • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3 • 33 MHz Max Clock Frequency • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Read Current: 7 mA (typical) – Standby Current: 8 µA (typical) • Flexible Erase Capability – Uniform 4 KByte sectors – Uniform 32 KByte overlay blocks • Fast Erase and Byte-Program: – Chip-Erase Time: 70 ms (typical) – Sector- or Block-Erase Time: 18 ms (typical) – Byte-Program Time: 14 µs (typical) • Auto Address Increment (AAI) Programming – Decrease total chip programming time over Byte-Program operations • End-of-Write Detection – Software Status • Hold Pin (HOLD#) – Suspends a serial sequence to the memory without deselecting the device • Write Protection (WP#) – Enables/Disables the Lock-Down function of the status register • Software Write Protection – Write protection through Block-Protection bits in status register • Temperature Range – Commercial: 0°C to +70°C – Industrial: -40°C to +85°C – Extended: -20°C to +85°C • Packages Available – 8-lead SOIC 150 mil body width for SST25LF020A – 8-lead SOIC 200 mil body width for SST25LF040A – 8-contact WSON (5mm x 6mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION SST’s serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SST25LF020A/040A SPI serial flash memories are manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The splitgate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST25LF020A/040A devices significantly improve performance, while lowering power consumption. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25LF020A/040A devices operate with a single 3.03.6V power supply. The SST25LF020A devices are offered in an 8-lead SOIC 150 mil body width (SA) package. The SST25LF040A devices are offered in an 8-lead SOIC 200 mil body width (S2A) package. All densities are offered in the 8-contact WSON package. See Figure 1 for the pin assignments. ©2006 Silicon Storage Technology, Inc. S71242-05-000 1/06 1 The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Data Sheet FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X - Decoder SuperFlash Memory Y - Decoder Control Logic I/O Buffers and Data Latches Serial Interface 1242 B1.0 CE# SCK SI SO WP# HOLD# ©2006 Silicon Storage Technology, Inc. S71242-05-000 1/06 2 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Data Sheet PIN DESCRIPTION CE# SO WP# VSS 1 2 8 7 VDD HOLD# SCK SI CE# SO WP# VSS 1 8 VDD HOLD# SCK SI 2 7 Top View 3 4 6 5 1242 08-soic P1.0 3 Top View 6 4 5 1242 08-wson P2.0 8-LEAD SOIC FIGURE 1: PIN ASSIGNMENTS TABLE 1: PIN DESCRIPTION Symbol Pin Name SCK Serial Clock Functions 8-CONTACT WSON To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To temporarily stop serial communication with SPI flash memory without resetting the device. To provide power supply (3.0-3.6V). T1.0 1242 SI SO CE# WP# HOLD# VDD VSS Serial Data Input Serial Data Output Chip Enable Write Protect Hold Power Supply Ground ©2006 Silicon Storage Technology, Inc. S71242-05-000 1/06 3 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Data Sheet PRODUCT IDENTIFICATION TABLE 2: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST25LF020A SST25LF040A 00001H 00001H 43H 44H T2.0 1242 DEVICE OPERATION The SST25LF020A/040A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25LF020A/040A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. Data BFH 00000H MEMORY ORGANIZATION The SST25LF020A/040A SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay blocks. CE# MODE 3 MODE 3 MODE 0 SCK SI SO MODE 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 1242 F02.0 HIGH IMPEDANCE FIGURE 2: SPI PROTOCOL ©2006 Silicon Storage Technology, Inc. S71242-05-000 1/06 4 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Data Sheet Hold Operation HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 3 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 18 for Hold timing. SCK HOLD# Active Hold Active Hold Active 1242 F03.0 FIGURE 3: HOLD CONDITION WAVEFORM Write Protection SST25LF020A/040A provides software Write protection. The Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled. TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUSREGISTER (WRSR) INSTRUCTION WP# L L H BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed T3.0 1242 ©2006 Silicon Storage Technology, Inc. S71242-05-000 1/06 5 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A Data Sheet Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or TABLE 4: SOFTWARE STATUS REGISTER Bit 0 1 2 3 4:5 6 Name BUSY WEL BP0 BP1 RES AAI Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP1, BP0 are read-only bits 0 = BP1, BP0 are read/writable Default at Power-up 0 0 1 1 0 0 Read/Write R R R/W R/W N/A R Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. 7 BPL 0 R/W T4.0 1242 Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable L