(SST174 - SST177) P-Channel JFET Switch

P-Channel JFET Switch CORPORATION J174 – J177 / SST174 – SST177 FEATURES ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise specified) Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . . 30V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC Operating Temperature Range . . . . . . . . . . . -55oC to +135oC Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . . 300oC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350mW Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/ oC NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. • Low Insertion Loss • No Offset or Error Generated By Closed Switch - Purely Resistive - High Isolation Resistance From Driver • Short Sample and Hold Aperture Time • Fast Switching • Analog Switches • Choppers • Commutators PIN CONFIGURATION APPLICATIONS ORDERING INFORMATION Part SOT-23 G TO-92 Package Temperature Range J174-J177 Plastic TO-92 -55oC to +135oC SST174-SST177 Plastic SOT-23 -55oC to +135oC For Sorted Chips in Carriers see 2N5114 series. D S S D G PRODUCT MARKING (SOT-23) SST174 P04 P05 P06 P07 SST175 SST176 SST177 5508 CORPORATION ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified) SYMBOL PARAMETER Gate Reverse Current (Note 1) Gate Source Cutoff Voltage Gate Source Breakdown Voltage Drain Saturation Current (Note 2) Drain Cutoff Current (Note 1) Drain-Source ON Resistance Drain-Gate OFF Capacitance Source-Gate OFF Capacitance Drain-Gate Plus Source Gate ON Capacitance Turn On Delay Time Rise Time Turn Off Delay Time Fall Time 5.5 5 J174 J175 J176 J177 UNITS TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX IGSS 1 1 1 1 nA VDS = 0, VGS = 20V VGS(off) 10 3 6 1 4 0.8 2.25 V VDS = -15V, ID = -10nA BVGSS 30 30 30 30 VDS = 0, IG = 1µA IDSS -20 -135 -7 -70 -2 -35 -1.5 -20 mA VDS = -15V, VGS = 0 ID(off) -1 -1 -1 -1 nA Ω VDS = -15V, VGS = 10V rDS(on) 85 125 250 300 VGS = 0, VDS = -0.1V Cdg(off) 5.5 5.5 5.5 VDS = 0, VGS = 10V Csg(off) 5.5 5.5 5.5 5.5 pF f = 1MHz (Note 3) Cdg(on) + Csg(on) 32 32 32 32 VDS = VGS = 0 td(on) tr td(off) tf 2 5 5 10 o 5 10 10 20 15 20 15 20 20 25 20 25 ns Switching Time Test Conditions (Note 3) J174 J175 J176 VDD -10V -6V -6V VGS(off) 12V 8V 3V RL 560Ω 12kΩ 5.6kΩ VGS(on) 0V 0V 0V J177 -6V 3V 10kΩ 0V NOTES: 1. Approximately doubles for every 10 C increase in TA. 2. Pulse test duration -300µs; duty cycle ≤3%. 3. For design reference only, not 100% tested.