Digitally Controlled 8 x 2 Audio Mixer

a FEATURES Each of 8 Inputs Can Be Assigned to Either or Both Outputs Voltage Inputs and Outputs – No Need For External Amplifiers Each Input Provides 63 dB of Attenuation in 1 dB Steps, Plus Mute –82 dBu Signal-to-Noise Ratio (0 dBu = 0.775 V rms) +10 dBu of Headroom 0.007% THD+N (Unity Gain, @ 1 kHz, 0 dBu) Power-Up/System Mute Feature Industry-Standard 3-Wire Serial Interface Data Out Terminal Permits Daisy Chaining of Multiple SSM2163s Single or Dual Supply Operation 28-Pin Plastic DIP and SOIC Package APPLICATIONS Multimedia System Mixing Audio Mixing Consoles Broadcast Equipment Intercom/Paging Systems Musical Instruments V IN1 DCA DCA Digitally Controlled 8 2 Audio Mixer SSM2163 SIMPLIFIED BLOCK DIAGRAM SSM2163 V IN2 VOLTAGE REFERENCE GENERATOR V IN3 DCA VCC VEE ACOM AGND V IN4 DCA VOUTL V IN5 DCA OUTPUT SWITCHING NETWORK VOUTR V IN6 DCA SYSTEM MUTE DATA OUT SHIFT REGISTER AND ADDRESS DECODER CLK DATA LD WRITE DGND VDD VSS V IN7 DCA GENERAL DESCRIPTION V IN8 DCA The SSM2163 provides eight audio inputs, each of which can be mixed under digital control to a stereo output. Each input channel can be attenuated up to 63 dB in 1 dB intervals, plus fully muted. Additionally, any input can be assigned to either or both outputs. A standard 3-wire serial interface is employed, plus a Data Out terminal to facilitate daisy chaining of multiple mixer ICs. No external components are required for normal operation. Excellent audio performance is attained. The SSM2163 has a signal-to-noise ratio of –82 dBu (0 dBu = 0.775 V rms), with 10 dBu of headroom resulting in total dynamic range of 92 dBu. Total harmonic distortion plus noise is 0.007% at 1 kHz with all levels set at unity gain. DCA: DIGITALLY CONTROLLED ATTENUATOR The SSM2163 can be operated from single (+5 V to +14 V) or dual (± 4 V to ± 7 V) supplies, and is housed in 28-pin plastic DIP and SOIC packages. The SSM2163 is an ideal companion product to the Analog Devices family of stereo codecs in high performance multimedia systems requiring mixing of multiple signals. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 SSM2163–SPECIFICATIONS5 V, A = 0 dB, V = 0 dBu = 0.775 V rms, f (V = ELECTRICAL SPECIFICATIONS Parameter AUDIO PERFORMANCE Noise Headroom Total Harmonic Distortion Plus Noise Conditions VIN = GND, 20 kHz Bandwidth Clip Point = 1% THD+N 2nd and 3rd Harmonics Only AV = 0 dB AV = –20 dB AV = 0 dB, VS = +5 V, Single Supply S V IN AUDIO = 1 kHz, fCLK = 250 kHz, RL = 100 k , –40 C < TA < +85 C, unless otherwise noted. Typical specifications apply at TA = +25 C.) Min Typ –82 +10 0.007 0.02 0.035 Max Units dBu dBu 0.03 % % % kΩ dB ANALOG INPUT Input Impedance VOLUME CONTROL Step Size Gain Error 7 10 1.0 15 Gain Match Error Relative to Same Channel 0 dB Attenuation –20 dB Attenuation –40 dB Attenuation Channel-to-Channel; Same Level Setting 0 dB Attenuation –20 dB Attenuation –40 dB 0.1 0.1 0.25 0.01 0.05 0.4 64 15 500 4 5000 50 1.0 dB dB Mute Attenuation ANALOG OUTPUT Output Impedance Output Current Minimum Resistive Load Maximum Capacitive Drive Offset Voltage CONTROL SECTION Logic Input LO Logic Input HI Logic Input Current Logic Out LO Logic Out HI Timing Characteristics REFERENCE (ACOM) Output Voltage Output Impedance Load Regulation POWER SUPPLIES Supply Voltage Range Supply Current Power Supply Rejection Ratio Specifications subject to change without notice. dB dB dB dB Ω µA kΩ pF mV 0.8 V V µA V V THD = 1% Channel Muted 2.0 Logic LO or HI IOUT = 0.2 mA IOUT = 0.2 mA See Timing Diagram VS = +10 V (Single Supply) –0.5 mA ≤ IL ≤ +0.5 mA (Single Supply) Dual Supply Single Supply VS = +10 V (Single Supply) Delta Gain ±4 +5 8 0.005 1 0.4 2.4 4.7 5.0 10 0.2 5.3 V Ω % V V mA dB/V ±7 +14 15 –2– REV. 0 SSM2163 Timing Description Timing Symbol tCL tCH tDS tDH tCW tWC tLW tWL tL tW3 tPD Description Input Clock Pulse Width Input Clock Pulse Width Data Setup Time Data Hold Time Positive CLK Edge to End of Write Write to Clock Setup Time End of Load Pulse to Next Write End of Write to Start of Load Load Pulse Width Load Pulse Width (3-Wire Mode) Propagation Delay from Rising Clock to SDO Transition (RL = 220 kΩ, CL = 20 pF) Min 50 50 25 35 25 35 20 20 250 250 10 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns 80 160 NOTES 1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the positive edge. 2. For SPI or microwire three-wire bus operation, tie LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic internal LD signal.) 3. If an idle HI clock is used, t CW and tWL are measured from the final negative transition to the idle state. 4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain levels. Refer to the Address/Data Decoding Truth Table. 5. Data must be sent MSB first. 1 CLK 0 1 DATA 0 1 WRITE & LOAD 0 D7 D6 D5 D4 D3 D2 D1 D0 tCL 1 CLK 0 tCH tDS 1 DATA 0 tDH tCW tW3 tWC 1 WRITE & LOAD 0 tPD 1 SDO 0 Figure 1. Three-Wire Mode Timing Diagram REV. 0 –3– SSM2163 1 CLK 0 1 DATA 0 1 WRITE 0 1 LD 0 D7 D6 D5 D4 D3 D2 D1 D0 tCL 1 CLK 0 tCH tDS 1 DATA 0 tDH tCW 1 WRITE 0 tWC tWL tL tLW 1 LOAD 0 tPD 1 SDO 0 Figure 2. Four-Wire Mode Timing Diagram –4– REV. 0 SSM2163 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 8 V Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C THERMAL CHARACTERISTICS PIN CONFIGURATIONS Epoxy Plastic DIP (P-Suffix) and SOIC (S-Suffix) DGND 1 VSS 2 DATA OUT 3 VDD 4 VIN1 5 NC (SHIELD) 6 28 SYSTEM MUTE 27 DATA IN 26 CLK 25 WRITE SSM2163 24 LD TOP VIEW 23 NC (SHIELD) VIN3 7 (Not to Scale) 22 VIN2 21 NC (SHIELD) 20 VIN4 19 NC (SHIELD) 18 VIN6 17 AGND 16 VIN8 15 VOUTR NC (SHIELD) 8 VIN5 9 VCC 10 VIN7 11 Thermal Resistance2 28-Pin Plastic DIP (SSM2163P) θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin SOIC (SSM2163S) θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSISTOR COUNT 48°C/W 22°C/W 68°C/W 20°C/W VEE 12 ACOM 13 VOUTL 14 Number of Transistors . . . . . . . . . . . . . . . . . . 1711 MOSFETs 447 BJTs ESD RATINGS 883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 1000 V NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 θJA is specified for worst-case conditions, i.e., θJA is specified for device in socket for P-DIP and device soldered in circuit board for SOIC package. ORDERING GUIDE Model SSM2163P SSM2163S Temperature Range –40°C to +85°C –40°C to +85°C Package Description Plastic DIP SOIC Package Option N-28 R-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2163 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– SSM2163 PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic DGND VSS DATA OUT VDD VIN1 NC (Shield) VIN3 NC (Shield) VIN5 VCC VIN7 VEE ACOM VOUTL VOUTR VIN8 AGND VIN6 NC (Shield) VIN4 NC (Shield) VIN2 NC (Shield) LD WRITE CLK Data In SYSTEM MUTE Function Digital Ground. Digital Negative Supply. Serial data output clocked on positive clock edge. Connect DATA OUT to DATA IN pin to daisy-chain multiple SSM2163s. Output levels are VDD to DGND. Digital Positive Supply. Audio Signal Input 1. Shield Pin. Should be tied to AGND to minimize crosstalk. Audio Signal Input 3. Shield Pin. Should be tied to AGND to minimize crosstalk. Audio Signal Input 5. Analog Positive Supply. Audio Signal Input 7. Analog Negative Supply. Analog Common Voltage. Provides a buffered voltage output halfway between VCC and VEE for use as a pseudo ground in single supply applications. Left Audio Output. Right Audio Output. Audio Signal Input 8. Analog Ground. Audio Signal Input 6. Shield Pin. Should be tied to AGND to minimize crosstalk. Audio Signal Input 4. Shield Pin. Should be tied to AGND to minimize crosstalk. Audio Signal Input 2. Shield Pin. Should be tied to AGND to minimize crosstalk. Load Data. Write