Balanced Line Driver

a FEATURES Transformer-Like Balanced Output Drives 10 V RMS Into a 600 Load Stable When Driving Large Capacitive Loads and Long Cables Low Distortion 0.006% typ 20 Hz–20 kHz, 10 V RMS into 600 High Slew Rate 15 V/ s typ Low Gain Error (Differential or Single-Ended); 0.7% typ Outputs Short-Circuit Protected Available In Space-Saving 8-Pin Mini-DIP Package Low Cost APPLICATIONS Audio Mix Consoles Distribution Amplifiers Graphic and Parametric Equalizers Dynamic Range Processors Digital Effects Processors Telecommunications Systems Industrial Instrumentation Hi-Fi Equipment VIN Balanced Line Driver SSM2142 FUNCTIONAL BLOCK DIAGRAM 50Ω +OUT FORCE +OUT SENSE 10kΩ – OUT SENSE 50Ω – OUT FORCE ALL RESISTORS 30kΩ UNLESS OTHERWISE INDICATED GND 10kΩ GENERAL DESCRIPTION The SSM2142 is an integrated differential-output buffer amplifier that converts a single-ended input signal to a balanced output signal pair with high output drive. By utilizing low noise thermally matched thin film resistors and high slew rate amplifiers, the SSM2142 helps maintain the sonic quality of audio systems by eliminating power line hum, RF interference, voltage drops, and other externally generated noise commonly encountered with long audio cable runs. Excellent rejection of common-mode noise and offset errors is achieved by laser trimming of the onboard resistors, assuring high gain accuracy. The carefully designed output stage of the SSM2142 is capable of driving difficult loads, yielding low distortion performance despite extremely long cables or loads as low as 600 Ω, and is stable over a wide range of operating conditions. Based on a cross-coupled, electronically balanced topology, the SSM2142 mimics the performance of fully balanced transformer-based solutions for line driving. However, the SSM2142 maintains lower distortion and occupies much less board space than transformers while achieving comparable common-mode rejection performance with reduced parts count. The SSM2142 in tandem with the SSM2141 differential receiver establishes a complete, reliable solution for driving and receiving audio signals over long cables. The SSM2141 features an Input Common-Mode Rejection Ratio of 100 dB at 60 Hz. Specifications demonstrating the performance of this typical system are included in the data sheet. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 SSM2142–SPECIFICATIONS noted. Typical characteristics apply to operation at T = +25 C.) A (VS = 18 V, –40 C ≤ TA ≤ +85 C, operating in differential mode unless otherwise Min Typ 10 ± 750 5.8 5.98 5.94 0.7 60 –38 –35 80 –45 –40 0.006 –93.4 +93.4 15 2 5.7 Max ± 900 Units kΩ µA dB dB % dB dB dB % dBu dBu V/µs 250 50 mV mV V 55 7.0 Ω mA mA Parameter INPUT IMPEDANCE INPUT CURRENT GAIN, DIFFERENTIAL GAIN, SINGLE-ENDED GAIN ERROR, DIFFERENTIAL POWER SUPPLY REJECTION RATIO STATIC OUTPUT COMMON-MODE REJECTION OUTPUT SIGNAL BALANCE RATIO TOTAL HARMONIC DISTORTION Plus Noise SIGNAL-TO-NOISE RATIO HEADROOM SLEW RATE OUTPUT COMMON-MODE VOLTAGE OFFSET1 DIFFERENTIAL OUTPUT VOLTAGE OFFSET DIFFERENTIAL OUTPUT VOLTAGE SWING OUTPUT IMPEDANCE SUPPLY CURRENT OUTPUT CURRENT, SHORT CIRCUIT Symbol ZIN IIN Conditions VIN = ± 7.071 V Single-Ended Mode RL = 600 Ω PSRR OCMR SBR THD+N SNR HR SR VOOS VOOD VS = ± 13 V to ± 18 V See Test Circuit; f = 1 kHz See Test Circuit; f = 1 kHz 20 Hz to 20 kHz, VO = 10 V rms, RL = 600 Ω VIN = 0 V CLIP Level = 10.5 V rms RL = 600 Ω RL = 600 Ω VIN = ± 7.071 V –250 –50 ± 13.8 45 25 15 ± 14.14 50 5.5 70 ZO ISY ISC Unloaded, VIN = 0 V 60 NOTES 1 Output common-mode offset voltage can be removed by inserting dc blocking capacitors in the sense lines. See Applications Information. Specifications subject to change without notice. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Output Short Circuit Duration (Both Outputs) . . . . Indefinite *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* PIN CONNECTIONS 8-Pin Plastic DIP (P Suffix) 16-Pin Wide Body SOL (S Suffix) NC NC – FORCE – SENSE GROUND VIN NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC NC + FORCE + SENSE +V –V NC NC ORDERING GUIDE NC Model Operating Temperature Range Package Description Plastic DIP SOL Package Option N-8 R-16 SSM2142P –40°C to +85°C SSM2142S* –40°C to +85°C *For availability of SOIC package, contact your local sales office. –2– REV. B SSM2142 300Ω V OUT V 300 Ω 1 2 3 VS = 0V 4 8 7 6 5 300Ω 1 2 8 7 6 5 ∆VOUT VIN 300 Ω +18V –18V V CMR = 10V p–p 600Ω VIN = 10V p–p 3 4 +18V –18V 600 Ω V VOUT ∆VOUT OCMR = 20 LOG VCMR SBR = 20 LOG Figure 1. Output CMR Test Circuit Figure 2. Signal Balance Ratio (BBC Method) Test Circuit Typical Performance Characteristics 140 120 TA = +25°C VS = ±18V ∆VS = ±1V 100 –PSR 80 60 +PSR 12 TA = +25°C VS = ±18V RL = 600Ω DIFF. MODE 0.1% DISTORTION 0.01% DISTORTION 6 POWER SUPPLY REJECTION – dB OUTPUT VOLTAGE SWING – V rms 10 8 4 40 20 2 0 10 100 1k FREQUENCY – Hz 10k 100k 0 10 20 30 FREQUENCY – kHz 50 100 Figure 3. Power Supply Rejection vs. Frequency 12 TA = +25°C RL = 600Ω Figure 4. Maximum Output Voltage Swing vs. Frequency 6.5 TA = +25°C VIN = 0V NO LOAD 5.5 OUTPUT VOLTAGE SWING – V rms 10 6.0 8 0.1% DISTORTION 6 SUPPLY CURRENT – mA DIFF. MODE FREQ. = 20kHz 5.0 4 4.5 2 4.0 0 ±2 ±6 ±10 SUPPLY VOLTAGE – Volts ±14 ±18 3.5 ±2 ±6 ±10 SUPPLY VOLTAGE – Volts ±14 ±18 Figure 5. Output Voltage Swing vs. Supply Voltage Figure 6. Supply Current vs. Supply Voltage REV. B –3– SSM2142 THD PERFORMANCE The following data, taken from the THD test circuit on an Audio Precision System One using the internal 80 kHz noise filter, demonstrates the typical performance of a balanced pair system based on the SSM2142/SSM2141 chip set. Both differential and single-ended modes of operation are shown, under a number of output load conditions which simulate various application situations. Note also that there is no adverse effect on system performance when using the optional series feedback capacitors, which reject dc cable offsets in order to maintain optimal ac noise rejection. The large signal transient response of the system to a 100 kHz square wave input is also shown, demonstrating the stability of the SSM2142 under load. +18V 10µF* 4 6 7 2 8 1 A C V IN SSM 3 2142 5 RL B SSM 2141 VOUT Figure 9. THD+N vs. Frequency at Point B (Differential Mode) 10µF* R1 R2 –18V *USED ONLY IN THD PLOTS AS NOTED. ALL CABLE MEASUREMENTS USE BELDEN 8451 CABLE. Figure 7. THD Test Circuit Figure 10. THD+N vs. Frequency at Point A (Single Ended) Figure 8. THD+N vs. Frequency at Point B (Differential Mode) Figure 11. THD+N vs. Frequency at Point C (SSM2141 Output) –4– REV. B SSM2142 on-chip 50 Ω series damping resistors. The impedances in the output buffer pair are precisely balanced by laser trimming during production. This results in the high gain accuracy needed to obtain good common-mode noise rejection, and excellent separation between the offset error voltages common to the cable pair and the desired differential input signal. As shown in the test circuit, it is suggested that a suitable balanced, high input-impedance differential amplifier such as the SSM2141 be used at the receiving end for best system performance. The SSM2141 receiver output is configured for a gain of one half following the 6 dB gain of the SSM2142, in order to maintain an overall system gain of unity. In applications encountering a large dc offset on the cable or those wishing to ensure optimal rejection performance by avoiding differential offset error sources, dc blocking capacitors may be employed at the sense outputs of the SSM2142. As shown in the test circuit, these components should present as little impedance as possible to minimize low-frequency errors, such as 10 µF NP (or tantalum if the polarity of the offset is known). SYSTEM GROUNDING CONSIDERATIONS 100 90 100 90 10 0% Figure 12. 100 kHz Square Wave Observed at Point B (Differential Mode). VO = 10 V rms, R1 = R2 = ∞, RL = 600 Ω 10 0% Due to ground currents, supply variations, and other factors, the ground potentials of the circuits at each end of a signal cable may not be exactly equal. The primary purpose of a balanced pair line is to reject this voltage difference, commonly called “longitudinal error.” A measure of the ability of the system to reject longitudinal error voltage is output common-mode rejection. In order to obtain the optimal OCMR and noise rejection performance available with the SSM2142, the user should observe the following precautions: 1. The quality of the differential output is directly dependent upon the accuracy of the input voltage presented to the device. Input voltage errors developed across the impedance of the