(SSM-2122) Dynamic Range Processors/Dual VCA

a FEATURES 0.01% THD at +10 dBV In/Out 100 dB VCA Dynamic Range Low VCA Control Feedthrough 100 dB Level Detection Range Log/Antilog Control Paths Low External Component Count APPLICATIONS Compressors Expanders Limiters AGC Circuits Voltage-Controlled Filters Noise Reduction Systems Stereo Noise Gates Dynamic Range Processors/Dual VCA SSM2120/SSM2122 FUNCTIONAL BLOCK DIAGRAM V+ 36kΩ SIGNAL OUT CURRENT MIRRORS –VC +VC V+ V+ SIGNAL INPUT V+ 36kΩ IREF GENERAL DESCRIPTION V– The SSM2120 is a monolithic integrated circuit designed for the purpose of processing dynamic signals in various analog systems including audio. This “dynamic range processor” consists of two VCAs and two level detectors (the SSM2122 consists of two VCAs only). These circuit blocks allow the user to logarithmically control the gain or attenuation of the signals presented to the level detectors depending on their magnitudes. This allows the compression, expansion or limiting of ac signals, some of the primary applications for the SSM2120. PIN CONNECTIONS 22-Pin Plastic DIP (P Suffix) 16-Pin Plastic DIP (P Suffix) THRESH 1 1 LOG AV 1 2 CONOUT 1 3 SIGOUT 1 4 +VC1 5 CFT 1 6 22 GND 21 V+ 20 SIGOUT 2 19 +VC2 GND 1 SIGOUT 1 2 +VC1 3 CFT 1 4 16 GND 15 V+ 14 SIGOUT 2 SSM2120 18 CFT 2 13 +VC2 TOP VIEW –VC1 5 (Not to Scale) 12 CFT 2 11 –VC2 10 SIGIN 2 9 GND SSM2122 TOP VIEW 17 –VC2 –VC1 7 (Not to Scale) 16 SIGIN 2 15 RECIN 2 14 CONOUT 2 13 LOG AV 2 12 THRESH 2 SIGIN 1 6 IREF 7 V– 8 SIGIN 1 8 RECIN 1 9 IREF 10 V– 11 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 SSM2120/SSM2122–SPECIFICATIONS I (@V = 15 V, T = +25 C, ELECTRICAL CHARACTERISTICS unless otherwise noted) Parameter POWER SUPPLY Supply Voltage Range Positive Supply Current Negative Supply Current VCAs Max ISIGNAL (In/Out) Output Offset Control Feedthrough (Trimmed) Gain Control Range Control Sensitivity Gain Scale Factor Drift Frequency Response Off Isolation Current Gain THD (Unity-Gain) Noise (20 kHz Bandwidth) LEVEL DETECTORS (SSM2120 ONLY) Detection Range Input Current Range Rectifier Input Bias Current Output Sensitivity (At LOG AV Pin) Output Offset Voltage Frequency Response IIN = 1 mA p-p IIN = 10 µA p-p IIN = 1 µA p-p CONTROL AMPLIFIERS (SSM2120 ONLY) Input Bias Current Output Drive (Max Sink Current) Input Offset Voltage Specifications are subject to change without notice. S A REF = 200 A, +VC = –VC = GND (AV = 0 dB). 0 dB = 1 V rms SSM2120/SSM2122 Typ Max ± 18 10 –8 ± 350 ±8 +40 6 –3300 250 100 –0.5 0.005 –80 90 0.085 95 2800 4 3 ± 0.5 1000 50 7.5 ± 85 7.5 ± 0.5 ± 175 ± 4.2 ± 3.4 +0.5 0.04 Conditions Min ±5 Units V mA mA µA µA µV dB mV/dB ppm/°C kHz dB dB % dB dB µA p-p nA mV/dB mV 8 –6 ± 300 RIN = ROUT = 36 kΩ, –30 dB ≤ AV ≤ 0 dB Unity-Gain –85 ± 325 ±1 ± 750 Unity Gain or Less At 1 kHz +VC = –VC = 0 V +10 dBV IN/OUT RE: 0 dBV kHz 5.0 nA mA mV ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Operating Temperature Range . . . . . . . . . . . . –10°C to +55°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . 10 mA Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C Package Type 16-Pin Plastic DIP (P) 22-Pin Plastic DIP (P) θJA1 86 70 θJC 10 7 Units °C/W °C/W Model SSM2120 SSM2122 Temperature Range –10°C to +50°C –10°C to +50°C Package Description 22-Pin Plastic DIP 16-Pin Plastic DIP Package Option (N-22) (N-16) NOTE 1 θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for P-DIP. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2120/SSM2122 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –2– REV. C SSM2120/SSM2122 +VC1 SSM2122 |I IN | FULL WAVE RECTIFIER 2V V+ RECIN 1 THRESH 1 CONOUT 1 INPUT 1 OUTPUT 1 –VC1 +VC2 CFT 1 LOG AV 1 V– V+ |I IN | INPUT 2 OUTPUT 2 RECIN 2 FULL WAVE RECTIFIER 2V –VC2 CFT 2 THRESH 2 CONOUT 2 LOG AV 2 V– Figure 1. SSM2120 Block Diagram VOLTAGE-CONTROLLED AMPLIFIERS VCA PERFORMANCE The two voltage-controlled amplifiers are full Class A current in/current out devices with complementary dB/V gain control ports. The control sensitivities are +6 mV/dB and –6 mV/dB. A resistor divider (attenuator) is used to adapt the sensitivity of an external control voltage to the range of the control port. It is best to use 200 Ω or less for the attenuator resistor to ground. VCA INPUTS Figures 2a and 2b show the typical THD and noise performance of the VCAs over ±20 dB gain/attenuation. Full Class A operation provides very low THD. 0.03 REFERENCE PIN THD – % 0.003 –20 The signal inputs behave as virtual grounds. The input current compliance range is determined by the current into the reference current pin. 0.01 The reference current determines the input and output current compliance range of the VCAs. The current into the reference pin is set by connecting a resistor to V+. The voltage at the reference pin is about two volts above V– and the current will be –10 I REF [(V +) – ((V – ) + 2 V )] = RREF 0 GAIN – dB 10 20 The current consumption of the VCAs will be directly proportional to IREF which is nominally 200 µA. The device will operate at lower current levels which will reduce the effective dynamic range of the VCAs. With a 200 µA reference current, the input and output clip points will be ± 400 µA. In general: ICLIP = ± 2 IREF VCA OUTPUTS NOISE – dBV a. VCA THD Performance vs. Gain (+10 dBV In/Out @ 1 kHz) –70 –80 The VCA outputs are designed to interface directly with the virtual ground inputs of external operational amplifiers configured as current-to-voltage converters. The outputs must operate at virtual ground because of the output stage’s finite output impedance. The power supplies and selected compliance range determines the values of input and output resistors needed. As an example, with ± 15 V supplies and ±400 µA maximum input and output current, choose RIN = ROUT = 36 kΩ for an output compliance range of ± 14.4 V. Note that the signal path through the VCA including the output current-to-voltage converter is noninverting. –90 –20 –10 0 GAIN – dB 10 20 b. VCA Noise vs. Gain (20 kHz Bandwidth) Figure 2. Typical THD and Noise Performance REV. C –3– SSM2120/SSM2122 TRIMMING THE VCAs The control feedthrough (CFT) pins are optional control feedthrough null points. CFT nulling is usually required in applications such as noise gating and downward expansion. If trimming is not used, leave the CFT pins open. Trim Procedure 1. Apply a 100 Hz sine wave to the control point attenuator. The signal peaks should correspond to the control voltages which induce the VCAs maximum intended gain and at least 30 dB of attenuation. 2. Adjust the 50 kΩ potentiometer for the minimum feedthrough. (Trimmed control feedthrough is typically well under 1 mV rms when the maximum gain is unity using 36 kΩ input and output resistors.) Applications such as compressor/limiters typically do not require control feedthrough trimming because the VCA operates at unity-gain unless the signal is large enough to initiate gain reduction. In this case the signal masks control feedthrough. This trim is ineffective for voltage-controlled filter applications. LEVEL DETECTION CIRCUITS Note: It is natural to assume that with the addition of the averaging capacitor, the LOG AV output would become the average of the log of the absolute value of IIN. However, since the capacitor forces an ac ground at the emitter of the output transistor, the capacitor charging currents are proportional to the antilog of the voltage at the base of the output transistor. Since the base voltage of the output transistor is the log of the absolute value of IIN, the log and antilog terms cancel, so the capacitor becomes a linear integrator with a charging current directly proportional to the absolute value of the input current. This effectively inverts the order of the averaging and logging functions. The signal at the output therefore is the log of the average of the absolute value of IIN. USING DETECTOR PINS REC IN, LOGAV, THRESH AND CONOUT When applying signals to RECIN (rectifier input) an input series resistor should be followed by a low leakage blocking capacitor since RECIN has a dc voltage of approximately 2.1 V above ground. Choose RIN for a ± 1.5 mA peak signal. For ± 15 V operation this corresponds to a value of 10 kΩ. A 1.5 MΩ value of RREF from log average to –15 V will establish a 10 µA reference current in the logging transistor (Q1). This will bias the transistor in the middle of the detector’s dynamic current range in dB to optimize dynamic range and accuracy. The LOG AV outputs are buffered and amplified by unipolar drive op amps. The 39 kΩ, 1 kΩ resistor network at the THRESH pin provides a gain of 40. An attenuator from the CONOUT (control output) t