Technical Data Sheet Features
SSC P485 PL Transceiver IC
4MHZ
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VSSD TP0 VDDA SI C1 C2 SO VSSA RST* TS*
• • • • • •
Enables low-cost networking products Spread Spectrum Carrier™ communication technology 9600 baud data rate Simple interface Single +5 Volt power supply requirement 20 pin SOIC package
NC VSSD XIN XOUT VDDD ILD DI RO WL
SSC P485
16 15 14 13 12 11
Introduction
The Intellon SSC P485 PL Transceiver IC is a highly integrated spread spectrum communication transceiver for implementing low-cost networking products. The SSC P485 contains a Spread Spectrum Carrier™ (SSC) transceiver, signal conditioning circuitry, and a simple host interface. A minimum of external circuitry is required to connect the SSC P485 to the DC power line, twisted pair cable, or other communication medium. The inherent reliability of SSC signaling technology provides substantial improvement in network and communication performance over other low-cost communication methods. The SSC P485 is the ideal basic communications element for a wide variety of low-cost networking applications.
SSC P485 Block Diagram
RST* ILD RO
RX Interface Logic Data Decode Logic Tracking & Data Extraction Logic
WL
Summation Encoder Binary Shift Register
C2 C1
Comp Amp
SI SO
DI
TX Interface Logic
Waveform Generator
DAC
Buf
4 MHz XIN XOUT
Clock Circuit TS Control
TS*
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Revision 5 24000828
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SSC P485 PL Transceiver IC
Absolute Maximum Ratings (1)
Symbol
VDDMAX VIN TSTG TL
Parameter
DC Supply Voltage Input Voltage at any Pin Storage Temperature Lead Temperature (Soldering, 10 seconds)
Value
-0.3 to 7.0 VSS-0.3 to VDD+0.3 -65 to +150 300
Unit
V V °C °C
Notes: 1. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Recommended Operating Conditions
Symbol
VDD FOSC TA
Parameter
DC Supply Voltage Oscillator Frequency Operating Temperature Humidity (non-condensing)
Min
4.5 -40
Typical
5.0 12 ± 0.05% +25
Max
5.5 +85 95
Unit
V MHz °C %
Electrical Characteristics
Conditions: VDD = 4.5 to 5.5 V T= -40 to +85°C Symbol
VOH VOL VIH VIL IIL vSO IDD
Parameter
Minimum High-level Output Voltage Maximum Low-level Output Voltage (1) Minimum High-level Input Voltage Maximum Low-level Input Voltage Maximum Input Leakage Current SSC Signal Output Voltage (2) Total Power Supply Current
Min
2.4 2.0
Typical
Max
0.4 0.8 ±10
Units
V V V V µA VP-P mA
4 15
Notes: 1. TS* pin IOL = 4 mA, all other outputs IOL = 2 mA 2. ZL = 2K Ω || 10 pF
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SSC P485 PL Transceiver IC
SSC P485 Pin Assignments
Pin 1 2 3 4 5 6 7 Mnemonic 4MHZ NC VSSD XIN XOUT VDDD ILD Name 4 MHz Clock Out No Connect Digital Ground Crystal Input Crystal Output Digital Supply Idle Line Detect Description 4 MHz clock output available for host microcontroller. Digital ground reference. Connected to external crystal to excite the IC’s internal oscillator and digital clock. Connected to external crystal to excite the IC’s internal oscillator and digital clock. 5.0 VDC ± 10% digital supply voltage with respect to VSSD. Digital output, active high. Logic 1 state indicates 10 bit times of idle line, logic 0 indicates detection of carrier or non-idle line. Digital input. After the preamble, a low on DI (SPACE) transmits a superior2 state on SO, a high on DI (MARK) transmits a superior1 state on SO. Digital output. After the preamble and assuming standard polarity: if superior1 state is detected on SI, RO will be high (MARK), if superior2 state is detected on SI, RO will be low (SPACE). Digital input. Logic 1 (default, internal pullup) selects 10-bit frame (START, eight data bits, STOP), logic 0 selects 11-bit frame (START, nine data bits, STOP). Active low digital output. Enables the external output amplifier when driven high. Tri-states the external output amplifier when driven low. Active low digital input. RST* asynchronously forces RO and ILD outputs to a high state and TS* to a low state. RST* can be asserted anytime during normal operation to force the reset state. RST* must be active (low) for 1 µsec after VDDD and VDDA stabilize and the crystal oscillator stabilizes to guarantee the internal reset state. See Figure 10. Analog ground reference. Analog signal output. Tri-state enabled with internal signal. Connection for 680pF capacitor to ground. Connection for 680pF capacitor to ground. Analog signal input. 5.0 VDC ± 10% analog supply voltage with respect to VSSA. Reserved pin for testing. Digital ground reference.
8
DI
Driver Input
9
RO
Receiver Output
10
WL
Word Length
11
TS*
Tristate
12
RST*
Reset
13 14 15 16 17 18 19 20
VSSA SO C2 C1 SI VDDA TP0 VSSD
Analog Ground Signal Output Capacitor 2 Capacitor 1 Signal Input Analog Supply Test Point 0 Digital Ground
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SSC P485 PL Transceiver IC
SSC P485 Application Examples
The SSC P485 may be used in a wide variety of applications. A typical node connecting to the medium is shown in Figure 1. A gateway between an RS485 twisted pair network and a DC power line network is shown in Figure 2. A multi-point network application with gateways using the SSC P485 is illustrated in Figure 3. Figure 4 presents a host interface flow diagram showing the major steps necessary to transmit and receive messages using the P485 IC.
Single W ire SSC P111 Power Line Media Interface
WR
DI SSC P485 PL Transceiver
SO
Microprocessor based Control Logic
output filter
medium coupler
RD
RO
TS* SI input filter
ILD
Figure 1. SSC P485 Typical Node
Transmit Enable #1 RXD #1 TXD #1 Twisted Pair Single W ire
RS-485 Transceiver
A TXRDY #1 D RXRDY #1 RD #1 W R #1 RXD #1 R RE* DE
UART
TXD #1
+ B
Microprocessor based Control Logic
DATA 0-7
RD #2 W R #2 TXRDY #2 RXD #2 RXRDY #2 RO TXD #2 DI SSC P485 PL Transceiver
SO
output filter
SSC P111 Power Line Media Interface
medium coupler
UART
TS* SI input filter
ILD ILD
Figure 2. SSC P485 Gateway
July 1998 4 Revision 5 24000828
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SSC P485 PL Transceiver IC
P111 IC
DC power line
P111 IC
host micro
P485 IC
P485 IC
host micro
gateway
gateway
RS485 IC
gate way micro
P111 IC
P111 IC
P485 IC
P485 IC
gate way micro
RS485 IC
RS485 device
RS485 device
RS485 device
RS485 device
RS485 device
RS485 device
Figure 3. SSC P485 Multi-point Network Application
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ADVANCE INFORMATION
SSC P485 PL Transceiver IC
Entry
No
message to transmit?
Yes
ILD==logic 1?
Yes
write 1st character to UART
UART indicates receive character available?
No
Yes read character from UART
Yes
transmitted last character?
Yes
character transmitted==character received?
No write next character to UART No Yes
No UART indicates transmit buffer available? No ILD==logic 1? No
Yes message has been transmitted
store character in message
No
UART indicates receive character available?
Yes
read character from UART
Yes
UART indicates receive character available?
No
No
process message
Yes
1-1/2 char times of quiet since last character?
Figure 4. Host Interface Flow Diagram
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SSC P485 PL Transceiver IC
SSC P485 Power Line Interface
Analog data is transferred between the communication medium and the SSC P485 over the Signal In (SI) and Signal Out (SO) pins (refer to Figure 5). When transmitting, SSC “chirps” from the SSC P485 SO pin are filtered by the output filter to remove harmonic energy (distortion) from the transmit signal and then amplified by the SSC P111 Power Line Media Interface IC. The SSC P111 is a high-efficiency amplifier and tri-state switch specifically designed for use in power line network systems. The amplifier is powered down and its output set to a high impedance condition when the SSC P485 TS* signal is logic low, isolating the amplifier from the receive circuitry and reducing node power consumption during receive operation. When the SSC P485 TS* signal is logic high, the communication signal is routed to the communication medium through the coupling circuit (capacitor or transformer). When receiving, the communication signal passes through the coupling circuit and is filtered by the bandpass input filter. The resulting signal is then applied to the SSC P485 SI pin for processing. Refer to the application reference shown in Figure 14.
Single Wire
SO Host micro with internal UART TXD DI P485 IC TS* RXD RO SI
output filter
P111 IC
medium coupler
input filter
ILD ILD
Figure 5. SSC P485 Medium Coupling SSC P485 Message Format
The P485 requires the following message formatting:
Start bits Data bits Stop bits Character gap Message gap Message length
1, logic low 8 or 9 (default 8) 1, logic high 0-4 bit times 12 bit times minimum 1 character minimum
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SSC P485 PL Transceiver IC
Transmit/Receive Timing
The SSC P485 timing with contention resolution is shown below. The P485 generates a preamble based on the first character of the message. Contention resolution requires that the first character of the message be unique among all possible transmitters in the network. If the channel is available and the transmitter wins contention, a tracking sync sequence followed by a retransmission of the first character occurs. The P485 also echoes the first character back to the host allowing the host to determine that the channel was available and to continue transmitting the message. If the channel was unavailable (the transmitter lost contention), the SO line is tristated and the first character of the received message is passed to the host. The host determines that the channel was not available (transmitted first character does not match received first character), and the host enters the receive message mode. Once the end of message is detected, the P485 drives ILD high after 10 bit times to
