Silicon Germanium IF Receiver

Product Description The Sirenza Microdevices’ SRF-2016 is a quadrature demodulator RFIC designed for UHF and microwave receiver IF applications. This device features switchable gain control, high P1dB, and excellent I/Q amplitude and phase balance. Use of this highly integrated device can result in lower component count, a more compact assembly, and higher transceiver card yields. The device is packaged in an industry standard 16 pin TSSOP with exposed paddle for superb RF and thermal ground. The matte tin finish on Sirenza’s lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS compliant per EU directive 2002/95. This package is also manufactured with green molding compounds that contain no antimony trioxide nor halogenated fire retardants. SRF-2016 SRF-2016Z Pb RoHS Compliant & Green Package 200 - 600 MHz Silicon Germanium IF Receiver 16 pin TSSOP with Exposed Ground Pad Package Footprint: 0.197 x 0.252 inches (5.0 x 6.4 mm) Package Height: 0.039 inches (1.0 mm) Functional Block Diagram Product Features • BBIN BBIP VCC GC2 www.DataSheet4U.com 1 2 3 4 5 6 7 8 16 15 BBQP BBQN VCC LOP LON VEE VCC INN • • • Available in Lead Free, RoHS compliant, and Green packaging Gain control in 20dB steps Excellent I/Q amplitude and phase balance Output P1dB > +4 dBm over all gain settings 0/90 14 13 12 11 10 9 GC1 VEE Applications • VCC INP Digital and spread spectrum communication systems Cellular, PCS, DCS, 2G, 2.5G, 3G transceivers ISM band transceivers Point-to-point microwave receivers Broadband wireless systems • • • • Product Specifications – I/Q Output Parameters I/Q Output Frequency Range I/Q Output Amplitude Balance I/Q Output Phase Balance I/Q Output Common-mode Voltage I/Q Output Return Loss 50 ohm nominal differential output Additional Test Conditions Unit MHz dB deg V dB Min. DC -0.2 -2 2.5 20 Typ. Max. 500 0.2 2 Product Specifications – LO Input Parameters LO Frequency Range LO Input Level LO Return Loss 50 ohm nominal differential input, Note 1 Additional Test Conditions Unit MHz dBm dB Min. 200 -3 0 20 Typ. Max. 600 +3 Performance tests and ratings for Sirenza Microdevices' products were performed internally by Sirenza and measured using specific computer systems and/or components and reflect the approximate performance of the products as measured by those tests. Any difference in circuit implementation, test software, or test equipment may affect actual performance. The information provided herein is believed to be reliable at press time and Sirenza Microdevices assumes no responsibility for the use of this information. All such use shall be entirely at the user's own risk. Prices and specifications for Sirenza Microdevices' products are subject to change without notice. Buyers should consult Sirenza Microdevices' standard terms and conditions of sale for Sirenza's limited warranty with regard to its products. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any product for use in life-support devices and/or systems. Copyright 2006 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS 102137 Rev C SRF-2016 SiGe IF Receiver Product Specifications – IF Input Parameters IF Frequency Range INP/INN Return Loss INP/INN Common mode voltage Gain Input P1dB Input IP2 Input IP3 DSB Noise Figure Gain Input P1dB Input IP2 Input IP3 DSB Noise Figure Gain Input P1dB Input IP2 Input IP3 DSB Noise Figure Low gain setting GC1 = GC2 = 0V Medium gain setting GC1 = +5V GC2 = 0V High gain setting GC1 = GC2 = +5V 50 ohm nominal differential input, Note 2 Internally generated Test Conditions (see page 2) Unit MHz dB V dB dBm dBm dBm dB dB dBm dBm dBm dB dB dBm dBm dBm dB -7 10 10 -9 28 -27 Min. 200 20 2 30 -25 +13 -14 14 12 -7 +41 +3 17 -5 12 +49 +24 33 -3 14 32 Typ. Max. 600 Product Specifications – Miscellaneous Parameters Supply Voltage (VCC) Supply Current (ICC) Thermal Resistance GC1, GC2 Input VIL GC1, GC2 Input VIH GC1, GC2 Input Impedance Hot spot on die to lead Logic level zero Logic level one Additional Test Conditions Unit V mA ºC/W V V kohm 0 0.7xVCC 40 Min. +4.75 Typ. +5.0 195 35 45 0.3xVCC VCC Max. +5.25 Test Conditions VCC = +5VDC, T = +25ºC, LO Input = 0 dBm, 400 MHz, IF Input = 401 MHz Gain State Low Gain Medium Gain High Gain GC1 Voltage 0V +5V +5V GC2 Voltage 0V 0V +5V IF Power 0 dBm -20 dBm -40 dBm Absolute Maximum Ratings Parameters Supply Voltage LO Input IF Input Operating Temperature Storage Temperature Value 6.0 +10 +10 -40 to +85 -65 to +150 Unit VDC dBm dBm ºC ºC Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation the device voltage and current must not exceed the maximum operating values specified in the product specifications table. Note 1: To achieve 20 dB port match above 100 MHz, the parasitic inductance of the package must be matched out. Note 2: To achieve 20 dB of port match, the parasitic inductance of the package, board, and L4, L5 must be matched out at the center frequency with a series capacitor. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS 102137 Rev C SRF-2016 SiGe IF Receiver Package Dimensions Dimensions in inches (mm) 0.193 (4.9) 0.207 (5.25) 0.004 (0.1) 0.008 (0.2) 0.018 (0.45) 0.030 (0.75) Suggested PCB Pad Layout SRF 2016 Lot ID EXPOSED THERMAL PAD ZONE 0.118 (3.0) SQ. 0.252 (6.4) 0.169 (4.3) 0.177 (4.5) 0.049 (1.25) 0.012 (0.30) 0.118 (3.0) 0.024 (0.63) Part # Lot # 0.014 (0.35) NOTES: 1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 2. TOLERANCE ±0.1MM UNLESS OTHERWISE SPECIFIED. 3. COPLANARITY: 0.1MM 4. CONTROLLING DIMENSION IS MILLIMETER, CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT. 5. FOLLOWED FROM JEDEC MO-153. 0° 8° 0.031 (0.8) 0.041 (1.05) 0.118 (3.0) φ0.010 (0.25) via 0.028 (0.7) 0.0 0.006 (0.15) 0.026 (.65) 0.007 (0.19) 0.012 (0.30) 0.035 (0.9) 0.272 (6.9) all units are in inches (mm) - vias connect pad to underlying ground plane - Indicates metalization Pin Out Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function BBIN BBIP VCC GC2 GC1 VEE VCC INP INN VCC VEE LON LOP VCC BBQN BBQP Description Baseband I-axis output (-) Baseband I-axis output (+) Positive power supply Gain control input, stage 2 Gain control input, stage 1 Ground Positive power supply IF input (+) IF input (-) Positive power supply Ground LO input (-) LO input (+) Positive power supply Baseband Q-axis output (-) Baseband Q-axis output (+) self-biasing self-biasing self-biasing; AC-couple self-biasing; AC-couple self-biasing; AC-couple self-biasing; AC-couple 5V CMOS levels 5V CMOS levels self-biasing self-biasing Additional Comments Part Number Ordering Information Number SRF-2016 SRF-2016Z Reel Size 7” 7” Devices/Reel 1000 1000 Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. 303 South Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS 102137 Rev C SRF-2016 SiGe IF Receiver The Sirenza SRF-2016 is a variable gain I-Q demodulator designed for use in receiver IF sections, as shown in the figure below. It consists of five subcircuits: two cascaded switched gain stages, a matched pair of mixers, and a LO quadrature generator. This part is also available in a lower frequency version, the SRF-1016. The gain stages are broadband differential amplifiers each with a digital control pin to set the gain. The gain control pins act independently of each other. Since the amplifiers have approximately the same gain, setting GC1 high and GC2 low results in approximately the same gain as setting GC1 low and GC2 high. The former setting is preferred because it offers better noise figure. The IF input is differential with internal bias circuitry to set the common mode voltage. The use of blocking capacitors to facilitate AC coupling is highly recommended to avoid changing the common mode voltage. Either input may be driven singleended if the other input is connected to ground through an AC short such as a 1000 pF capacitor. This typically results in slightly lower input P1dB. The two matched mixers are configured with the quadrature LO generator to provide in-phase and quadrature baseband outputs. These can be fed through ADCs to a DSP engine, or can be fed into a low frequency 90 degree hybrid for image rejection. Alternatively, the IF signal can be extracted from the BBI port by injecting DC into the LO port. The LO and IF ports offer a differential 50 ohm impedance. The package (and in the case of the input port, the parallel L-R network) adds inductance that tends to degrade return loss. This can easily be matched out with a series capacitor. The 8.2 pF capacitor on the evaluation board is appropriate for 400 MHz operation; larger capacitors should be used for lower frequencies. The SRF-2016 has high gain at UHF frequencies, so instability can result if there is poor power supply decoupling or undesired coupling from the input to the output. The following considerations should be observed when laying out a PC board: • Follow the general layout of the evaluation board, keeping the power supply decoupling capacitors as close to the package as possible. • The back of the package, the two ground pins and the decoupling capacitors should connect directly to ground, preferably to a large dedicated ground plane. • Use the parallel L-R circuits on the input pins. • Ensure that the input signal tracks are routed far from the output tracks. • The Vcc pins are not internally connected, so all must be connected together externally with the specified decoupling capacitors. The figures on page 5 illustrate a typ