Catalog Number 276-1784
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AN EXCLUSIVE RADIO SHACK SERVICE TO THE EXPERIMENTER
SPO256 NARRATORTM SPEECH PROCESSOR
Stand Alone Operation with Inexpen-
sive Support Components
Wide Operating Voltage
Word, Phrase, or Sentence Library,
Expandable to 491 K of ROM Directly
Simple Interface to Most Microcom-
puters or Microprocessors
Supports L.P.C. Synthesis: Formant
Synthesis: Allophone Synthesis
The SPO256 (Speech Processor) is a single
chip N-Channel MOS LSI device that is
able, using its stored program, to synthe-
size speech or complex sounds.
The achievable output is equivalent to a
flat frequency response ranging from 0
to 5 kHz, a dynamic range of 42dB, and
a signal to noise ratio of approximately
The SP0256 incorporates four basic
A software programable digital filter
that can be made to model a VOCAL
A 16K ROM which stores both data
and Instructions (THE PROGRAM).
A MICROCONTROLLER which con-
trols the data flow from the ROM to
the digital filter, the assembly of the
“word strings” necessary for linking
speech elements together, and the
amplitude and pitch information to
excite the digital filter.
A PULSE WIDTH MODULATOR that
creates A digital output which is con-
verted to an analog signal when fil-
tered by an external low pass filter.
Allophone Based Speech Processor
One example of a preprogramed SPO256
is the AL2 pattern.
Allophone Usage with a
The SPO256-AL2 requires the use of a
processor to concatenate the speech
sounds to form words.
The SPO256 is controlled using the ad-
dress pins (A1-A8), ALD (Address Load),
and SE (Strobe Enable). The object for
controlling the chip is to load an address
into It which contains the desired allo-
phone. The speech data for the allophone
set is contained within the internal 16K
ROM of the SPO256-AL2.
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This particular application (Allophone Set)
requires only six address Pins (A1-A6) to
address all the 69 allophones plus five
pauses, a total of 64 locations. For
simplicity, since only six address pins are
needed to address the 64 locations, pins A7
and A8 can be tied low (to ground) and now
any further references to the address bus
will Include A1-A6 end A7=A8=0
There are two modes available for loading an
address into the chip. SE (Strobe Enable)
controls the mode that will be used.
Mode 0 (SE=0) will latch is an address when
any one or more of the address pins makes
a low to high transition. For example, to load
the address one (1), A2 to A6=0 and A1 is
pulsed high. To load the address twelve (12
octal), A1=A3=A5=A6=0, A2 and A4 are
pulsed high simultaneously. (Note that an
address of zero cannot be loaded using this
Mode 1 (SE=1) will latch in an address using
the ALD pln. First, setup the desired
address on the address bus (A1-A6) and
low. Any address can be loaded using this
mode, but certain setup and hold times are
then pulse ALD required (refer to the
attached timing diagram for the specific
Two microprocessor interface pins are
available for quick loading of addresses.
They are LRQ and SBY. LRQ (Load
Request) tells the processor when the input
buffer is full. SBY (Stand By) tells the
processor that the chip has stopped talking
and no new address has been loaded. Either
interface pin can be used when
concatenating allophones. LRQ is an active
low signal, when LRQ goes low it is time to
load a new address to the chip. If LRQ is
high, then simply wait for It to go low before
loading the address. SBY will stay high until
an address is loaded, then it will go low and
stay low until all the internal instructions
(Speech Code) from that one address are
completed. Once this signal goes high, It is
time to load a new address. Since speech
does not require very fast address loading, it
would be acceptable to use SBY to interface
to the processor.
SPO256 BLOCK DIAGRAM
2K x 8 BIT
SERIAL COEFFICIENT TRANSFER
VOCAL TRACT MODEL
(12 POLE DIGITAL
ALD SE LRQ SBY
A8 8 BIT A1
To end a word using allophones it is
necessary to load a pause to complete the
word. For example, the word “TWO”
All pins with respect to Vss.........-0.3 to 8.0V
Storage Temperature.............-25°C to 125°C
Clock - Crystal Frequency ............3.120 MHz
Operating Temperature (Ta).......0°C to 70°C
DC CHARACTERlSTlCS/SPO 256
can be implemented using the following
allophones, TT2-VW2-PA1. PA1 is actually
not an allophone but a pause which is
needed to end the word.
*Exceeding these ratings could cause permanent
damage to the device. This is a stress rating only and
functional operation of this device at these conditions
is not im-plied. Operating ranges are specified in
Standard Condi-tions. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Data labeled "typical" is presented for design
guidance only and is not guaranteed
Sym Min Typ Max Units
A1-A8, ALD, SERIN, TEST, SE
RESET, SBY RESET
SBY, Digital Out, C1, C2, C3,
LRQ, ROM DIS, ROM CLK,
OSC 2 (Output)
90 mA TA = 25ºC, VD1 , VDD = 7.0V
Reset & SBY Reset high.
All outputs floating.
21 mA Same as above.
0 Volts bias, f = 3.12 MHz
VPIN = 7.0V Other Pins = 0.0V
I OL = 0.72ma (2LS TTL Loads)
IOH = -50 µa (2LS TTL Loads)
When driven from external source.
OSC 1 (Input) = 3.90 V MIN
OSC 1 (Input) = 0.60 V MAX
PIN NUMBER 1 N A M E
3 ROM DISABLE
Cl, C2, C3
A 8 , A7, A6, A5,
A4. A3. A2. A 1
21 SER IN
A logic 0 resets that portion of the SP
powered by VDD. Must be returned to a
logic 1 for normal operation.
For use with an external serial speech
ROM, a logic 1 disables the external
Output control lines for use with an ex-
ternal serial speech ROM. Refer to the
SPR016 Data Sheet for details.
Power supply for all portions of the SP
except the microprocessor interface logic.
STANDBY. A logic 1 output Indicates
that the SP is inactive and VDD can be
powered down externally to conserve
power. When the SP is reactivated by an
address being loaded, SBY will go to a
LOAD REQUEST. LRQ is a logic 1
output whenever the input buffer is
full. When LRQ goes to a logic 0, the in-
put port may be loaded by placing the 8
address bits on A1-A8 and pulsing the
8 bit address which defines any one of
256 speech entry points.
SERIAL ADDRESS OUT. This output
transfers a 16-bit address serially to an
external speech ROM.
STROBE ENABLE. Normally held in a
logic 1 state. When tied to ground, ALD
Is disabled and the SP will automatic-
ally latch in the address on the input bus
approximately lus after detecting a logic
1 on any address line.
ADDRESS LOAD. A negative pulse on
this input loads the 8 address bits into
the input port. The negative edge of this
pulse causes LRQ to go high.
SERIAL IN. This is an E-bit serial data
input from an external speech ROM.
Pin Functions Continued
I PIN NUMBER
This pin should be grounded for normal
Power supply for the microprocessor in-
terface logic and controller.
Pulse width modulated digital speech
output which, when filtered by a 5KHz
low pass filter and amplified, will drive a
STANDBY RESET. A logic 0 resets the
microprocessor interface logic and the
address latches. Must be returned to a
logic 1 for normal operation.
This is a 1.56MHz clock output used
to drive an external serial speech ROM.
XTAL IN. Input connection for a
XTAL OUT. Output connection for a
A few basic linguistic concepts will help
you start your own library of “allo-
phone words”. (See Table 1 for the Gen-
eral Instrument Allophone Dictionary).
The allophone speech
First, there is no one-to-one correspon-
synthesis technique provides the user
dence between written letters and speech
with the ability to synthesize an un-
sounds; secondly, speech sounds are
limited vocabulary at a very low bit
acoustically different depending upon
rate. Fifty-nine discrete speech sounds
their position within a word; and lastly,
(called allophones) are five pauses are
the human ear may perceive the same
stored at different addresses in the
acoustic signal differently in the context
SPO256 internal ROM. Each speech
of different sounds.
sound was excised from a word and an-
alyzed using linear predictive coding
The first point compares to the problem
(LPC). Any English word or phrase can
that a child encounters when learning to
be created by addressing the appropri-
read. Each sound in a language may be
ate combination of allophones and
represented by more than one letter and,
pauses. Since there Is a total of 64 address
conversely each letter may represent more
locations each requires a 6 bit address.
than one sound. (See the examples in
Assuming that speech contains 10 to
Table 2.) Because of these spelling ir-
12 sounds per second, allophone syn-
regularities, it is necessary to think in
thesis requires addressing less than 100
terms of sounds, not letters, when using
bits per second.
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