Synchronous Buck Controller

Solved by SP6133 TM Synchronous Buck Controller FEATURES ■ 5V to 24V Input step down converter ■ Up to 30A output capability ■ Highly integrated design, minimal components ■ UVLO Detects Both VCC and VIN ■ Overcurrent circuit protection with auto-restart ■ Power Good Output, ENABLE Input ■ Maximum Controllable Duty Cycle Ratio up to 92% ■ Wide BW amp allows Type II or III compensation ■ Programmable Soft Start ■ Fast Transient Response ■ High Efficiency: Greater than 95% possible ■ Available in Lead Free, RoHS Compliant 6-Pin QFN package ■ External Driver Enable/Disable ■ U.S. Patent #6,922,04 www.DataSheet4U.com UVIN 16 GL PGND GND 1 2 3 4 5 15 14 BST 13 12 GH 11 10 9 8 SWN ISP ISN VCC SP6133 16 Pin QFN 3mm x 3mm VFB 6 VIN 7 COMP EN PWRGD VIN 10-15V GND 3.3V 0-10A GND DESCRIPTION The SP633 is a synchronous step-down switching regulator controller optimized for high efficiency. The part is designed to be especially attractive for single supply step down conversion from 5V to 24V. The SP633 is designed to drive a pair of external NFETs using a fixed 300 kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown, output short circuit protection, and overcurrent protection with auto restart. The device also features a PWRGD output and an enable input. The SP633 is available in a space saving 6-pin QFN and offers excellent thermal performance. TYPICAL APPLICATION CIRCUIT C5 0.1uF DBST CVCC 10uF BAT54WS VIN VCC R3 10K POWERGOOD NC PWRGD UVIN EN ENABLE BST GH SWN SC5018-2R7M 2.7uH, 15A, 4.1mOhm MB, Si4320DY 4 mOhm, 30V CBST 0.1uF MT, Si4394DY 9.75 mOhm, 30V C1 22uF C2 22uF VOUT C3 100uF C4 100uF SP6133 GL RS1 5.11K RS2 5.11K GND PGND ISP ISN CSP 6.8nF CSS 47nF RZ3 1K CS 0.1uF COMP CP1 39 pF VFB SS R1 68.1K, 1% CZ3 560pF CF1 22pF CZ2 1500pF RZ2 23.2K R2 21.5K, 1% Note: Die attach paddle is internally connected to GND. Oct 24-06 Rev L SP633 Synchronous Buck Controller © 2006 Sipex Corporation  SS ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VCC .................................................................................................. 6V VIN .............................................................................................. 24.5V BST................................................................................................ 30V BST-SWN ........................................................................................ 7V SWN .................................................................................-2V to 24.5V GH ..........................................................................-0.3V to BST+0.3V GH-SWN.......................................................................................... 6V All other pins ............................................................-0.3V to VCC+0.3V Peak Output Current < 10µs GH,GL ............................................................................................. 2A Storage Temperature ................................................... -65°C to 150°C Power Dissipation ........................................................................... W ESD Rating ........................................................................... 2kV HBM Thermal Resistance.............................................................. 41.9°C/W Unless otherwise specified: -40°C < TAMB < 85°C, 4.5V < VCC < 5.5V, BST=VCC, SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC = 0µF, CCOMP = 0.µF, CGH = CGL = 3.3nF, CSS = 50nF, RPWRGD = 0KΩ. ELECTRICAL SPECIFICATIONS PARAMETER QUIESCENT CURRENT VIN Supply Current VCC Supply Current BST Supply Current PROTECTION: UVLO VCC UVLO Start Threshold VCC UVLO Hysteresis UVIN Start Threshold UVIN Hysteresis VIN Start Threshold VIN Hysteresis Enable Pullup Current Error Amplifier Reference Error Amplifier Reference Over Line & Temperature COMP Sink Current COMP Source Current VFB Input Bias Current COMP Common Mode Output Range COMP Pin Clamp Voltage MIN TYP MAX UNITS CONDITIONS .5 .5 0.2 3.0 3.0 0.4 4.5 250 2.65 400 0.0 mA mA mA V mV V mV V mV µA 0.808 0.82 230 -70 00 3.2 3.8 V V µA µA nA V V VFB = 0.7V Apply voltage to UVIN pin Apply voltage to UVIN pin UVIN Floating UVIN Floating Apply voltage to EN pin 2x Gain Config. VFB = V (no switching) VFB = V (no switching) VFB = V (no switching) 4.00 50 2.35 200 9.0 4.25 200 2.50 300 9.5 300 0.4 ERROR AMPLIFIER REFERENCE 0.792 0.800 0.788 0.800 70 -230  .9 3.2 50 -50 50 3.0 3.5 Oct 24-06 Rev L SP633 Synchronous Buck Controller © 2006 Sipex Corporation 2 Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = PGND = 0.0 V, UVIN = 3.0V, CVCC = 0.µF, CCOMP = 0.µF, CGH = CGL = 3.3nF, CSS = 50nF. ELECTRICAL SPECIFICATIONS PARAMETER Ramp Offset Ramp Amplitude GH Minimum Pulse Width Maximum Controllable Duty Ratio Maximum Duty Ratio Internal Oscillator Frequency MIN .7 0.80 92 00 255 -6 .0 TYP 2.0 .0 50 MAX UNITS CONDITIONS 2.3 .20 00 V V ns % % Guaranteed by design TA = 25˚C CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH 300 -0 2.0 345 -4 3.0 kHz µA mA Fault Present VIN = 6 to 23V, ILOAD = 0mA to 30mA IVCC = 30mA TIMERS: SOFTSTART SS Charge Current: SS Discharge Current: VCC LINEAR REGULATOR VCC Output Voltage Dropout Voltage 4.6 250 -0 5.0 500 -7.5 2.0 .0 5.4 750 -5 4.0 0 V mV % % mA VFB = 0.7V, VPWRGD = 0.2V Measured VREF (0.8V) - VFB Measured ISP - ISN POWER GOOD OUTPUT Power Good Threshold Power Good Hysteresis Power Good Sink Current PROTECTION: SHORT CIRCUIT & THERMAL Short Circuit Threshold Voltage Overcurrent Threshold Voltage ISP, ISN Common Mode Range Hiccup Timeout Thermal Shutdown Temperature Thermal Hysteresis 0.2 54 0 85 35 220 45 0 0.25 60 0.3 66 3.3 270 55 V mV V ms ˚C ˚C Guaranteed by design Oct 24-06 Rev L SP633 Synchronous Buck Controller © 2006 Sipex Corporation 3 Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = PGND = GND = 0.0V, UVIN = 3.0V, CVCC = 0.µF, CCOMP = 0.µF, CGH = CGL = 3.3nF, CSS = 50nF. ELECTRICAL SPECIFICATIONS PARAMETER GH & GL Rise Times GH & GL Fall Times GL to GH Non Overlap Time SWN to GL Non Overlap Time GH & GL Pull Down Resistance Driver Pull Down Resistance Driver Pull Up Resistance MIN TYP MAX UNITS 35 30 45 25 5 50 .5 2.5 50 40 70 40 85 .9 3.9 ns ns ns ns KΩ Ω Ω CONDITIONS Measured 0% to 90% Measured 90% to 0% GH & GL Measured at 2.0V Measured SWN = 00mV to GL = 2.0V OUTPUT: NFET GATE DRIVERS BLOCk DIAGRAM VCC 5 COMP SS NON SYNC. STARTUP COMPARATOR GL HOLD OFF VFBINT 4 VCC VCC 10 uA SOFTSTART INPUT SS 8 0.1V VPOS POS REF Gm FAULT Gm ERROR AMPLIFIER 1.6 V PW M LOO P RESET DOMINANT R Q FAULT S QPWM 13 BST VFB 12 GH SYNCHRONOUS DRIVER 11 SWN 1 GL FAULT RAMP = 1V 300 kHZ 2 PGND CLK CLOCK PULSE GENERATOR 2.8 V VCC 16 REFERENCE CORE 0.8V REF OK 1.3 V VCC 1 uA ENABLE EN 6 1.7V ON 1.0V OFF COMPARATOR 4.25 V ON 4.05 V OFF VCC UVLO POWER FAULT FAULT THERMAL SHUTDOWN 145ºC ON 135ºC OFF SET DOMINANT S Q HICCUP FAULT 3 GND 5V LINEAR REGULATOR VPOS VIN 14 VFBINT 140KΩ UVIN 15 2.50 V ON 2.20 V OFF 50KΩ 0.25V SHORT CIRCUIT DETECTION R CLK 220ms Delay OVER CURRENT DETECTION COUNTER CLR REF OK Power Good VFB 0.74 V ON 0.72 V OFF 7 PWRGD VIN UVLO 10 ISP 9 ISN 60 mV UVLO COMPARATORS THERMAL AND O VER CURRENT PRO TECTION Oct 24-06 Rev L SP633 Synchronous Buck Controller © 2006 Sipex Corporation 4 PIN PIN # NAME  2 3 4 5 6 7 8 9 0  2 3 4 5 6 GL DESCRIPTION PIN DESCRIPTION High current driver output for the low side NFET switch. It is always low if GH is high or during a fault. Resistor pull down ensures low state at low voltage. Ground Pin. The power circuitry is referenced to this pin. Return separately from other ground Ground pin. The control circuitry of the IC is referenced to this pin. Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error Amplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode. Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM ground or VFB to stabilize the voltage mode loop. PGND traces to the (-) terminal of Cout. GND VFB COMP comparator. An optimal filter combination is chosen and connected to this pin and either EN Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is internally pulled to VCC with a µA current source. Power Good Output. This open drain output is pulled low when VOUT is outside of the Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft start rate based on the 0µA source current. The SS pin is held low via a mA (min) current during all fault conditions. Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE and NSENSE. Offset accuracy +0%. Positive Input for the Inductor Current Sense. Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFET transistors. High current driver output for the high side NFET switch. It is always low if GL is high or during a fault. High side driver supply pin. Connect BST to the external boost diode and capacitor as shown in the Application Schematic of page . High side driver is connected between BST pin and SWN pin. Supply Input -- supplies power to the internal LDO. Under