Half Bridge 500VDC Driver

® SP601 July 1998 N HDRAW RT WIT SOLETE PA SS OB S PROCE DESIGN O NEW N File Number 2429.5 Features Half Bridge 500VDC Driver The SP601 is a smart power high voltage integrated circuit (HVIC) optimized to drive MOS gated power devices in halfbridge topologies. It provides the necessary control and management for PWM motor drive, power supply, and UPS applications. • Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V • Ability to Interface and Drive Standard and Current Sensing N-Channel Power MOSFET/IGBT Devices • Creation and Management of a Floating Power Supply for Upper Rail Drive • Simultaneous Conduction Lockout • Overcurrent Protection • Single Low Current Bias Supply Operation • Latch Immune CMOS Logic • Peak Drive in Excess of 0.5A Ordering Information PART NUMBER SP601 TEMPERATURE RANGE -40oC to +85oC PACKAGE 22 Lead Plastic DIP Pinout SP601 (PDIP) TOP VIEW FAULT 1 ITRIPSEL 2 VBIAS 3 VDD 4 VSS 5 TRIPL 6 CL1 7 G2L 8 G1L 9 D1L 10 VDF 11 UP/ 22 DOWN 21 ENABLE 20 NC 19 D1U 18 G1U 17 G2U 16 CL2 15 TRIPU 14 PHASE 13 VOUT 12 VBS Functional Block Diagram VBS 12 D1U VBIAS 3 VDD 4 VDF 11 10Ω RND IONT LEVEL SHIFT 3.5Ω RBS UV LOCK OUT + IOFFT S R 19 G1U 18 Q G2U 17 TRIPU 15 CL2 16 UPPER LOWER UP/DN 22 ITRIPSEL S R PHASE Q 14 3.5Ω RO 13 10 VOUT D1L ENABLE 21 CMOS TIMING AND CONTROL VOUT SENSE AND FILTER FAULT Q S R IONB IOFFB S R G1L Q 9 G2L 8 FAULT 750Ω RF 1 UV LOCK OUT + - TRIPL 6 CL1 7 FILTER ITRIPSEL 2 ITRIPSEL S R Q VSS 5 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved SP601 Absolute Maximum Ratings Full Temperature Range, All Voltage Referenced to V SS Unless Otherwise Noted. Note 1, Note 2. Low Voltage Power Supply, V BIAS (Note 1). . . . . . . . . . . . . . 18VDC Floating Low Voltage Boot Strap . . . . . . . . . . . . . . . . . . . . . . 18VDC Power Supply to Phase, VBS Low Voltage Signal Pins Fault, ITRIPSEL, VDD , TRIPL , CL1 , G2L . . . -0.5VDC to VDD +0.5 G1L, D1L, VDF , TOP, BOT CL2, TRIPU , G1U, G2U, D1U to Phase . . . .-0.5VDC to VBS+0.5 High Voltage Pins Phase, VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500VDC (VBS , VOUT , TRIPU , CL2, G2U and D1U: 0V-18V Higher Than Phase) Dynamic High Voltage Rating Phase,. . . . . . . . . . . . . 10,000V/µs DVPHASE/DT Thermal Resistance, Junction-to-Ambient θJA Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Package Power Dissipation at TA = +85oC, PO Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Operating Ambient Temperature Range, TA . . . . . . .-40oC to +85oC Storage Temperature Range, TS . . . . . . . . . . . . . .-40oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC Thermal Information NOTES: 1. Care must be taken in the application of VBIAS as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (RND). Prolonged high peak currents may result if +15VDC is applied abruptly and/or if the local bypass capacitor CDD is large. It is suggested that CDD be ≤ 10MFD. If it is desirable to switch the 15VDC source or if a CDD is larger, additional series impedance may be required. 2. Consult factory for additional package offerings. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (VBIAS = 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to VSS Except TRIPU , CL2, G1U, D1U, and V BS Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE SYMBOL TEMP +25oC -40oC to +85oC IBIAS Quiescent Current (All Inputs Low) IBIAS Quiescent Current (VOUT ≥ VBIAS , and All Inputs Low) IBS Quiescent Current Bootstrap Supply ENABLE Threshold Level IBIAS IBIAS IBS VTOP VBOT V TRIPSEL VTRIP L/U L PARAMETER DC CHARACTERISTICS Input Current (5V < VTOP , VBOT , VTRIPSEL < 15V) MIN TYP MAX UNITS IIN 7 6.95 7 6.95 7 6.95 90 90 110 109 9 9.7 5 4.7 500 450 20 30 1.7 1.7 1.7 1.7 875 900 8 8 8 8 8 8 105 105 130 130 10 10.5 7 7 760 760 30 33 2.05 2.1 2.05 2.1 1000 1060 9 9.1 9 9.1 9 9.1 125 127 150 152 11.5 11.8 9 9.6 1000 1100 µA µA mA mA mA mA µA µA V V V V V V mV mV % % V V V V Ω Ω +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC H UP/DN Threshold Level Current Trip Select Threshold Level Trip Lower and Upper Comparator Threshold Level - Normal (ITRIPSEL = VSS) Trip Lower and Upper Comparator Threshold Level - Boost (ITRIPSEL = VDD) % of Measured VTRIP L/UN Under Voltage Lockout Thresholds (VDD and V BS ) Phase Out of Status Voltage Threshold (PHASE) N VTRIP L/U B VLOCK VOSVT RF Faultbar Impedance at IFBAR = 1mA 2 SP601 Electrical Specifications (VBIAS = 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to VSS Except TRIPU , CL2, G1U, D1U, and V BS Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE (Continued) SYMBOL RSO L/U RSI L/U RBS RND ILK TEMP +25oC -40oC to +85oC Upper/Lower Sink Impedances (ISINK = 10mA) Bootstrap Supply Current Limiting Impedance +25oC -40oC to +85oC +25oC -40oC to +85oC Noise Dropping Resistor Impedance +25oC -40oC to +85oC High Voltage Leakage (500V VBS, VOUT, PHASE, TRIPU, CL2, G1U, G2U, and D1U to VSS. All other Pins at VSS) Miller Clamp Diodes; D1U and D1L (ID = 10mA) Noise Clamping Zeners; CL2 and CL1 (IZ = 10mA) Noise Clamping Zeners; CL2 and CL1 (IZ = 50mA) VOUT Limiting Resistance +25oC MIN 12 7 8 5 2 1.4 6 5.4 TYP 17 17 12 12 3.5 3.5 10 10 1 MAX 23 29 16 20 5 5.6 14 14.6 3 PARAMETER Upper/Lower Source Impedances (ISOURCE = 10mA) UNITS Ω Ω Ω Ω Ω Ω Ω Ω µA VD1U/L VCL2/1-LOW VCL2/1HIGH +25oC +25oC -40oC to +85oC +25oC +25oC -40oC to +85oC 0.4 6.35 6.15 7.0 2 1.4 0.9 6.61 6.61 8.5 3.5 3.5 1.4 6.85 7.15 8.0 5 5.6 V V V V Ω Ω RO NOTE: Maximum Steady State ÷ 15V DC Supply Current = IBIAS L ÷ IBS Switching Specifications (All Referenced to VSS , Except: TRIPU , Cl2, G1U, G2U, and D1U Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE) SYMBOL tREF tOFF PARAMETER Refresh One Shot Timer TEMP +25oC -40oC to +85oC Delay Time of Trip I/U Voltage (ITRIPSEL low) to G2U/G2L Low (50% Overdrive Delay Time of Trip I Voltage (ITRIPSEL low) to Faultbar Low Delay Time of Phase Out of Status to Faultbar Low (TOP High) Minimum Logic Input Pulse Width: TOP and BOTTOM Minimum G1U/G1L On Time TN MIN 200 180 2 1.85 2 1.85 500 400 300 275 1.6 1.5 1.3 1.05 2.5 2.1 2.5 2.1 0.75 0.60 TYP 350 350 3 3 3 3 700 700 430 430 2.3 2.4 2.0 2.1 3.2 3.3 3.2 3.3 1.0 1.1 MAX 500 540 4 4.35 4 4.35 900 1050 600 660 3.1 3.4 3.4 3.9 4.5 5.2 4.5 5.2 1.5 1.75 UNITS µs µs µs µs µs µs ns ns ns ns µs µs µs µs µs µs µs µs µs µs +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC tFN tOSVF tMINIW tON tOFF tON tON tON Minimum Pulsed Off Time, G2U/G2L Turn On Delay Time of G1U (BISTATE MODE) D Turn On Delay Time of G1L (BISTATE MODE) D Turn On Delay Time of G1U (THREE-STATE MODE) D 3 SP601 Switching Specifications (All Referenced to VSS , Except: TRIPU , Cl2, G1U, G2U, and D1U Referenced to PHASE. DF: VDF to VBS, CF: VBS to PHASE) (Continued) SYMBOL tOND tOFFD tD.T. tR.T. tR U/L tF U/L TEMP +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC +25oC -40oC to +85oC Rise Time of Upper and Lower Driver (Load = 2000pF) Fall Time of Upper and Lower Driver (Load = 2000pF) +25oC -40oC to +85oC +25oC -40oC to +85oC PARAMETER Turn On Delay Time of G1L (THREE-STATE MODE) Turn Off Delay Time of G2U and G2L MIN 0.75 0.60 0.75 0.60 1.5 1.2 3.4 3.15 25 15 25 15 TYP 1.0 1.1 1.0 1.1 2.5 2.6 4.5 4.8 50 50 50 50 MAX 1.5 1.75 1.45 1.75 3.5 4 6.6 7.4 100 115 100 115 UNITS µs µs µs µs µs µs µs µs ns ns ns ns Minimum Dead Time: G1U OFF to G1L ON, or G1L off to G1U on (BISTATE MODE) Fault Reset Delay to Clear Faultbar Recommended Operating Conditions and Functional Pin Description (All Voltages Referenced to VSS, Unless Otherwise Noted. See Figure 1) PARAMETER FAULTBAR ITRIPSELECT VBIAS VDD VSS TRIP I CL1 G2L and G1L VDF VBS VOUT PHASE TRIPU CL2 G2U and G1U ENABLE UP/DN D1U D1L Open Drain Fault Indicator Output Digital Input Command to Increase TRIPL and TRIPU Threshold by 30% 14.5V to 16.5V with 15V nominal, ≅ 1.5mA DC BIAS Current CDD to VSS COMMON 100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output Lower Noise Clamp Zener Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER) Current Limiting Charging Resistor for Bootstrap Capacitor Power Supply Bootstrap Supply, Normally a Diode Drop Below VDD Voltage with Respect to the Floating PHASE Reference Load Connection Node Floating Reference Point for High Side Control Circuitry: VBS, TRIPU, CL2, G1U, G2U and D1U 100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive Upper Noise Clamp Zener Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER) Digital Input to ENABLE the UP/DN Command to Turn on Top/Bottom Devices Digital Input to Top/Bottom Device (If ENABLE is High) Miller Clamp UPPER to VBS Miller Clamp LOWER to VDD CONDITION 4 SP601 Timing Diagram ENABLE 1 0 UP/DOWN REFRESH ONE SHOT I ONB VALID BOTON IOFF T IONT IOFFB UPPER LOWER VOUT 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDC COM LOWER VOUT UPPER IONT IOFF B