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SN54HCT74, SN74HCT74 DUAL D TYPE POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
D D D D D D D
Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 40-µA Max ICC Typical tpd = 17 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible
SN54HCT74 . . . J OR W PACKAGE SN74HCT74 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
1CLR 1D 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 2CLR 2D 2CLK 2PRE 2Q 2Q
SN54HCT74 . . . FK PACKAGE (TOP VIEW)
1D 1CLR NC VCC 2CLR 1CLK NC 1PRE NC 1Q
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2D NC 2CLK NC 2PRE
1Q GND NC
NC − No internal connection
ORDERING INFORMATION
TA PDIP − N PACKAGE† Tube of 25 Tube of 50 SOIC − D −40 C 85°C −40°C to 85 C SOP − NS SSOP − DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP − PW CDIP − J −55 C 125°C −55°C to 125 C CFP − W Reel of 2000 Reel of 250 Tube of 25 Tube of 150 ORDERABLE PART NUMBER SN74HCT74N SN74HCT74D SN74HCT74DR SN74HCT74DT SN74HCT74NSR SN74HCT74DBR SN74HCT74PW SN74HCT74PWR SN74HCT74PWT SNJ54HCT74J SNJ54HCT74W SNJ54HCT74J SNJ54HCT74W HT74 HCT74 HT74 HCT74 TOP-SIDE MARKING SN74HCT74N
LCCC − FK Tube of 55 SNJ54HCT74FK SNJ54HCT74FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright 2004, Texas Instruments Incorporated
• DALLAS, TEXAS 75265
2Q 2Q
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SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
SN54HCT74, SN74HCT74 DUAL D TYPE POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
FUNCTION TABLE INPUTS PRE L H L H H CLR H L L H H CLK X X X ° ° D X X X H L OUTPUT Q H L H† H L Q L H H† L H
H H L X Q0 Q0 † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
logic diagram (positive logic)
PRE CLK C C C C Q TG C C D TG TG TG Q C CLR C C
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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SN54HCT74, SN74HCT74 DUAL D TYPE POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
recommended operating conditions (see Note 3)
SN54HCT74 MIN VCC VIH VIL VI VO ∆t/∆v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT74 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns
TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II ICC ∆ICC† Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOH = −20 µA IOH = −4 mA IOL = 20 µA IOL = 4 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 0.1 0.26 ±100 4 2.4 10 SN54HCT74 MIN 4.4 3.7 0.1 0.4 ±1000 80 3 10 MAX SN74HCT74 MIN 4.4 3.84 0.1 0.33 ±1000 40 2.9 10 V nA µA mA pF V MAX UNIT
IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 4.5 V fclock Clock frequency PRE or CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK↑ PRE or CLR inactive th Hold time, data after CLK↑ 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 16 14 18 16 12 11 0 0 0 0 TA = 25°C MIN MAX 27 30 24 21 27 24 18 16 0 0 0 0 SN54HCT74 MIN MAX 18 20 20 18 23 21 15 14 0 0 0 0 ns ns ns SN74HCT74 MIN MAX 22 24 MHz UNIT
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
SN54HCT74, SN74HCT74 DUAL D TYPE POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax PRE or CLR tpd CLK tt Q or Q Q or Q Q or Q FROM (INPUT) TO (OUTPUT) VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN 27 30 TA = 25°C TYP MAX 40 46 21 17 20 18 8 7 35 31 28 25 15 14 SN54HCT74 MIN 18 20 53 48 42 38 22 20 MAX SN74HCT74 MIN 22 24 44 40 35 31 19 17 ns ns MHz MAX UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS No load TYP 35 UNIT pF
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point CL = 50 pF (see Note A) Low-Level Pulse 3V Input 1.3 V tPLH In-Phase Output 1.3 V 10% tPHL 90% 1.3 V 10% tf 90% tr Out-ofPhase Output tPLH 1.3 V 10% 90% tr VOH VOL Data Input 1.3 V 0.3 V 1.3 V 0V tPHL 90% VOH Reference 1.3 V Input 10% V OL tf 3V 1.3 V 0V tsu 2.7 V tr th 2.7 V 3V 1.3 V 0.3 V 0 V tf High-Level Pulse 3V 1.3 V tw 3V 1.3 V 1.3 V 0V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PACKAGE OPTION ADDENDUM
6-Dec-2006
PACKAGING INFORMATION
Orderable Device JM38510/65352B2A JM38510/65352BCA JM38510/65352BDA SN
