OCTAL BUS TRANSCEIVERS AND REGISTERS

www.DataSheet4U.com SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178C – MARCH 1984 – REVISED MARCH 2003 D D D D D D Operating Voltage Range of 4.5 V to 5.5 V Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible SN54HCT646 . . . JT OR W PACKAGE SN74HCT646 . . . DW OR NT PACKAGE (TOP VIEW) D D D D Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads SN54HCT646 . . . FK PACKAGE (TOP VIEW) A7 A8 GND NC B8 CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 NC A4 A5 A6 DIR SAB CLKAB NC VCC CLKBA SBA 4 5 6 7 8 9 10 11 3 2 1 28 27 26 25 24 23 22 21 20 19 12 13 14 15 16 17 18 OE B1 B2 NC B3 B4 B5 NC – No internal connection description/ordering information The ’HCT646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’HCT646 devices. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers. ORDERING INFORMATION TA PDIP – NT –40°C to 85°C SOIC – DW CDIP – JT –55°C to 125°C CFP – W PACKAGE† Tube Tube Tape and reel Tube Tube ORDERABLE PART NUMBER SN74HCT646NT SN74HCT646DW SN74HCT646DWR SNJ54HCT646JT SNJ54HCT646W TOP-SIDE MARKING SN74HCT646NT HCT646 SNJ54HCT646JT SNJ54HCT646W LCCC – FK Tube SNJ54HCT646FK SNJ54HCT646FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B7 B6 1 www.DataSheet4U.com SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS description/ordering information (continued) The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be stored in one register and /or B data can be stored in the other register. When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS OE X X H H L L L DIR X X X X L L H CLKAB ↑ X ↑ H or L X X X CLKBA X ↑ ↑ H or L X H or L X SAB X X X X X X L SBA X X X X L H X A1– A8 Input Unspecified† Input Input disabled Output Output Input DATA I/O B1– B8 Unspecified† Input Input Input disabled Input Input Output OPERATION OR FUNCTION Store A, B unspecified† Store B, A unspecified† Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus SCLS178C – MARCH 1984 – REVISED MARCH 2003 L H H or L X H X Input Output Stored A data to B bus † The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178C – MARCH 1984 – REVISED MARCH 2003 BUS B 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X 22 SBA L 21 OE L 3 DIR H 1 CLKAB X 23 CLKBA X 2 SAB L BUS B 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H BUS B 22 SBA H X TRANSFER STORED DATA TO A AND/OR B BUS A REAL-TIME TRANSFER BUS B TO BUS A BUS B BUS A 21 OE X X H 3 DIR X X X 1 23 CLKAB CLKBA X ↑ X ↑ ↑ ↑ STORAGE FROM A, B, OR A AND B 2 SAB X X X 22 SBA X X X 21 OE L L Pin numbers shown are for the DW, JT, NT, and W packages. Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 BUS A 3 DIR L H BUS A 3 www.DataSheet4U.com SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS logic diagram (positive logic) OE 21 SCLS178C – MARCH 1984 – REVISED MARCH 2003 DIR CLKBA SBA CLKAB SAB 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 1D C1 B1 To Seven Other Channels Pin numbers shown are for the DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W (see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-3. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS178C – MARCH 1984 – REVISED MARCH 2003 recommended operating conditions (see Note 4) SN54HCT646 MIN VCC VIH VIL VI VO tt Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT646 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC† Ci Control inputs Control inputs A or B TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC IOH = –20 µA IOH = –6 mA IOL = 20 µA IOL = 6 mA VCC 4.5 45V 45V 4.5 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 ±0.01 0.1 0.26 ±100 ±0.5 8 2.4 10 SN54HCT646 MIN 4.4 3.7 0.1 0.4 ±1000 ±10 160 3 10 MAX SN74HCT646 MIN 4.4 3.84 0.1 0.33 ±1000 ±5 80 2.9 10 MAX UNIT V V nA µA µA mA pF † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock l k tw tsu th Clock frequency Pulse duration, CLKBA or CLKAB high or low duration 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V Setup ti S t time, A before CLKAB↑ or B b f b f before CLKBA↑ Hold time, A after CLKAB↑ or B after CLKBA↑ time 5.5 V 4.5 V 5.5 V 16 14 20 18 5 5 TA = 25°C MIN MAX 31 36 23 21 30 27 5 5 SN54HCT646 MIN MAX 22 24 19 17 25 23 5 5 SN74HCT646 MIN MAX 27 29 UNIT MHz ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 www.DataSheet4U.com SN54HCT646, SN7