OCTAL BUS TRANSCEIVERS

www.DataSheet4U.com SCLS019D − MARCH 1984 − REVISED AUGUST 2003 SN54HCT645, SN74HCT645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS D Operating Voltage Range of 4.5 V to 5.5 V D High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns SN54HCT645 . . . J OR W PACKAGE SN74HCT645 . . . DW, N, NS, OR PW PACKAGE (TOP VIEW) D D D D ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible True Logic SN54HCT645 . . . FK PACKAGE (TOP VIEW) A2 A1 DIR VCC A3 A4 A5 A6 A7 DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 OE B1 B2 B3 B4 B5 description/ordering information These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. ORDERING INFORMATION TA PDIP − N SOIC − DW −40 C 85°C −40°C to 85 C SOP − NS PACKAGE† Tube of 20 Tube of 25 Reel of 2000 Reel of 2000 Tube of 70 TSSOP − PW CDIP − J −55 C 125°C −55°C to 125 C CFP − W Reel of 2000 Reel of 250 Tube of 20 Tube of 85 ORDERABLE PART NUMBER SN74HCT645N SN74HCT645DW SN74HCT645DWR SN74HCT645NSR SN74HCT645PW SN74HCT645PWR SN74HCT645PWT SNJ54HCT645J SNJ54HCT645W SNJ54HCT645J SNJ54HCT645W HT645 HCT645 HCT645 TOP-SIDE MARKING SN74HCT645N LCCC − FK Tube of 55 SNJ54HCT645FK SNJ54HCT645FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A8 GND B8 B7 B6 Copyright  2003, Texas Instruments Incorporated 1 www.DataSheet4U.com SCLS019D − MARCH 1984 − REVISED AUGUST 2003 SN54HCT645, SN74HCT645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS FUNCTION TABLE INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation logic diagram (positive logic) OE 19 DIR 1 A1 2 18 B1 To Seven Other Transceivers absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SCLS019D − MARCH 1984 − REVISED AUGUST 2003 SN54HCT645, SN74HCT645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS recommended operating conditions (see Note 3) SN54HCT645 MIN VCC VIH VIL VI VO ∆t/∆v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT645 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC† Ci DIR or OE DIR or OE A or B TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC IOH = −20 µA IOH = −6 mA IOL = 20 µA IOL = 6 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 ±0.01 0.1 0.26 ±100 ±0.5 8 2.4 10 SN54HCT645 MIN 4.4 3.7 0.1 0.4 ±1000 ±10 160 3 10 MAX SN74HCT645 MIN 4.4 3.84 0.1 0.33 ±1000 ±5 80 2.9 10 V nA µA µA mA pF V MAX UNIT † This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis tt FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B A or B VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 16 14 25 22 26 23 9 8 22 20 46 41 40 36 12 11 SN54HCT645 MIN MAX 33 30 69 62 60 54 18 16 SN74HCT645 MIN MAX 28 25 58 52 50 45 15 14 ns ns ns ns UNIT PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 www.DataSheet4U.com SCLS019D − MARCH 1984 − REVISED AUGUST 2003 SN54HCT645, SN74HCT645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tt FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B A or B VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 20 18 36 30 17 14 30 27 59 53 42 38 SN54HCT645 MIN MAX 45 41 89 80 63 57 SN74HCT645 MIN MAX 38 34 74 67 53 48 ns ns ns UNIT operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per transceiver TEST CONDITIONS No load TYP 40 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SCLS019D − MARCH 1984 − REVISED AUGUST 2003 SN54HCT645, SN74HCT645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION VCC S1 RL PARAMETER tPZH ten 1 kΩ tPZL tPHZ tPLZ 1 kΩ RL CL 50 pF or 150 pF 50 pF 50 pF or 150 pF S1 Open Closed Open Closed −− Open S2 Closed Open Closed Open Open From Output Under Test CL (see Note A) Test Point S2 tdis tpd or tt LOAD CIRCUIT Input 1.3 V 0.3 V 2.7 V 2.7 V 3V 1.3 V 0.3 V 0 V tf tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3V Input 1.3 V tPLH In-Phase Output 1.3 V 10% tPHL Out-ofPhase Output 90% 1.3 V 10% tf 90% tr tPLH 1.3 V 10% 90% tr VOH VOL 1.3 V 0V tPHL 90% VOH 1.3 V 10% V OL tf Output Control (Low-Level Enabling) 3V 1.3 V tPZL 1.3 V 0V tPLZ ≈VCC 1.3 V 10% tPHZ 1.3 V 90% VOH ≈0 V VOL Output Waveform 1 (See Note B) tPZH Output Waveform 2 (See Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 www.DataSheet4U.com www.ti.com PACKAGE OPTION ADDENDUM 24-May-2007 PACK