OCTAL TRANSPARENT D-TYPE LATCHES

www.DataSheet4U.com SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 D D D D D D D D Operating Voltage Range of 4.5 V to 5.5 V High-Current 3-State Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 21 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Bus-Structured Pinout SN54HCT573 . . . J OR W PACKAGE SN74HCT573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) description/ordering information These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The ’HCT573 devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up at the D inputs. OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE SN54HCT573 . . . FK PACKAGE (TOP VIEW) 3D 4D 5D 6D 7D 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 OE VCC 1Q 2Q 3Q 4Q 5Q 6Q TOP-SIDE MARKING A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION TA PDIP – N SOIC – DW –40°C to 85°C SOP – NS SSOP – DB TSSOP – PW CDIP – J –55°C to 125°C CFP – W LCCC – FK PACKAGE† Tube Tube Tape and reel Tape and reel Tape and reel Tube Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74HCT573N SN74HCT573DW SN74HCT573DWR SN74HCT573NSR SN74HCT573DBR SN74HCT573PW SN74HCT573PWR SNJ54HCT573J SNJ54HCT573W SNJ54HCT573FK SNJ54HCT573FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8D GND LE 8Q 7Q HCT573 HCT573 HT573 HT573 2D 1D SN74HCT573N SNJ54HCT573J SNJ54HCT573W 1 www.DataSheet4U.com SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS description/ordering information (continued) OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z SCLS176E – MARCH 1984 – REVISED JULY 2003 logic diagram (positive logic) OE LE 1 11 C1 1D 2 1D 19 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 recommended operating conditions (see Note 3) SN54HCT573 MIN VCC VIH VIL VI VO ∆t/∆v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT573 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC† Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC IOH = –20 µA IOH = –6 mA IOL = 20 µA IOL = 6 mA VCC 4.5 45V 45V 4.5 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 ±0.01 0.1 0.26 ±100 ±0.5 8 2.4 10 SN54HCT573 MIN 4.4 3.7 0.1 0.4 ±1000 ±10 160 3 10 MAX SN74HCT573 MIN 4.4 3.84 0.1 0.33 ±1000 ±5 80 2.9 10 MAX UNIT V V nA µA µA mA pF † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC tw tsu th Pulse duration LE high duration, Setup time data before LE↓ time, Hold time, data after LE↓ time 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V TA = 25°C MIN MAX 20 17 10 9 5 5 SN54HCT573 MIN 30 27 15 14 5 5 MAX SN74HCT573 MIN 25 23 13 12 5 5 MAX UNIT ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 www.DataSheet4U.com SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) D tpd d LE ten tdis di tt Any Q Any Q Any Q Any Q TO (OUTPUT) Q VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 25 21 28 25 26 23 23 22 9 9 35 32 35 32 35 32 35 32 12 11 SN54HCT573 MIN MAX 53 48 53 48 53 48 53 48 18 16 SN74HCT573 MIN MAX 44 40 44 40 44 40 44 40 15 14 ns ns ns ns UNIT SCLS176E – MARCH 1984 – REVISED JULY 2003 OE OE switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) D tpd d LE ten tt Any Q Any Q Any Q TO (OUTPUT) Q VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 32 27 38 36 33 28 18 16 52 47 52 47 52 47 42 38 SN54HCT573 MIN MAX 79 71 79 71 79 71 63 57 SN74HCT573 MIN MAX 65 59 65 59 65 59 53 48 ns ns ns UNIT OE operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per latch TEST CONDITIONS No load TYP 50 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT573, SN74HCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS176E – MARCH 1984 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC S1 RL PARAMETER ten tPZH tPZL tPHZ tPLZ 1 kΩ RL 1 kΩ CL 50 pF or 150 pF 50 pF 50 pF or 150 pF S1 Open Closed Open Closed –– Open S2 Closed Open Closed Open Open From Output Under Test CL (see Note A) Test Point tdis S2 tpd or tt LOAD CIRCUIT Reference Input 3V 1.3 V 0V tsu th 2.7 V 3V 1.3 V 0.3 V 0 V tf High-Level Pulse 3V 1.3 V tw 1.3 V 0V 3V 1.3 V 1.3 V 0V VOLTAGE WAVEFORMS PULSE DURATIONS Low-Level Pulse Data Input 1.3 V 0.3 V 2.7 V tr VOLTAGE WAVEFORMS SETUP A