OCTAL D-TYPE FLIP-FLOPS

www.DataSheet4U.com SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 D D D D D D D Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible SN54HCT377 . . . J OR W PACKAGE SN74HCT377 . . . DW OR N PACKAGE (TOP VIEW) D D D Contain Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators SN54HCT377 . . . FK PACKAGE (TOP VIEW) 10 11 description/ordering information These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN. ORDERING INFORMATION TA PDIP – N –40°C to 85°C SOIC – DW CDIP – J –55°C to 125°C CFP – W LCCC – FK PACKAGE† Tube Tube Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74HCT377N SN74HCT377DW SN74HCT377DWR SNJ54HCT377J SNJ54HCT377W SNJ54HCT377FK TOP-SIDE MARKING SN74HCT377N HCT377 SNJ54HCT377J SNJ54HCT377W SNJ54HCT377FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4Q GND CLK 5Q 5D CLKEN 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 1D 1Q CLKEN VCC 8Q 2D 2Q 3Q 3D 4D 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 1 www.DataSheet4U.com SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE FUNCTION TABLE (each flip-flop) INPUTS CLKEN H L L X CLK X ↑ ↑ L D X H L X OUTPUT Q Q0 H L Q0 SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 logic diagram (positive logic) CLKEN 1 CLK 11 C1 1D 3 1D C1 2D 4 1D C1 3D 7 1D C1 4D 8 1D C1 5D 13 1D C1 6D 14 1D C1 7D 17 1D C1 8D 18 1D 2 1Q 5 2Q 6 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HCT377 MIN VCC VIH VIL VI VO tt Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise and fall) times VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT377 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II ICC ∆ICC‡ Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOH = –20 µA IOH = –4 mA IOL = 20 µA IOL = 4 mA VCC 4.5 V 4.5 V 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.30 0.001 0.17 ±0.1 0.1 0.26 ±100 8 2.4 10 SN54HCT377 MIN 4.4 3.7 0.1 0.4 ±1000 160 3 10* MAX SN74HCT377 MIN 4.4 3.84 0.1 0.33 ±1000 80 2.9 10 MAX UNIT V V nA µA mA pF IO = 0 One input at 0.5 V or 2.4 V, Other inputs at GND or VCC * On products compliant to MIL-PRF-38535, this parameter is not production tested. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 www.DataSheet4U.com SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock lk tw Clock frequency Pulse duration CLK high or low Data tsu Setup time before CLK↑ ↑ CLKEN high or low Data th Hold time data after CLK↑ ↑ CLKEN inactive or active 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 20 18 12 10 12 10 3 3 5 5 TA = 25°C MIN MAX 25 30 30 28 18 17 18 17 3 3 5 5 SN54HCT377 MIN MAX 17 19 25 23 15 14 15 14 3 3 5 5 ns ns SN74HCT377 MIN MAX 20 22 UNIT MHz ns SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54HCT377 PARAMETER FROM (INPUT) TO (OUTPUT) VCC 4.5 V 5.5 V CLK Any Any 4.5 V 5.5 V 4.5 V 5.5 V TA = 25°C MIN TYP MAX 25 30 31 37 15 12 8 6 30 28 15 14 MIN 17 19 45 40 22 21 MAX UNIT fmax tpd d tt MHz ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74HCT377 PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN fmax tpd d tt CLK Any Any 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 25 30 TA = 25°C TYP MAX 31 37 15 12 8 6 30 28 15 14 MIN 20 22 38 35 19 17 MAX UNIT MHz ns ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 30 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pF (see Note A) Low-Level Pulse 3V Input 1.3 V tPLH In-Phase Output 1.3 V 10% tPHL 90% 1.3 V 10% tf 90% tr Out-ofPhase Output tPLH 1.3 V 10% 90% tr VOH VOL Data Input 1.3 V 0.3 V 1.3 V 0V tPHL 90% VOH Reference 1.3 V Input 10% V OL tf 3V 1.3 V 0V tsu 2.7 V tr th 2.7 V 3V 1.3 V 0.3 V 0 V tf High-Level Pulse 3V 1.3 V tw 3V 1.3 V 1.3 V 0V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE