OCTAL BUFFERS AND LINE DRIVERS

www.DataSheet4U.com SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS SCLS174E − MARCH 1984 − REVISED AUGUST 2003 D Operating Voltage Range of 4.5 V to 5.5 V D High-Current Outputs Drive Up To 15 D D D D D D LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers SN54HCT240 . . . J OR W PACKAGE SN74HCT240 . . . DW, N, NS, OR PW PACKAGE (TOP VIEW) description/ordering information These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 SN54HCT240 . . . FK PACKAGE (TOP VIEW) 1A2 2Y3 1A3 2Y2 1A4 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 2Y4 1A1 1OE VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 ORDERING INFORMATION TA PDIP − N SOIC − DW −40 C 85°C −40°C to 85 C SOP − NS PACKAGE† Tube of 20 Tube of 25 Reel of 2000 Reel of 2000 Tube of 70 TSSOP − PW CDIP − J −55 C 125°C −55°C to 125 C CFP − W Reel of 2000 Reel of 250 Tube of 20 Tube of 85 ORDERABLE PART NUMBER SN74HCT240N SN74HCT240DW SN74HCT240DWR SN74HCT240NSR SN74HCT240PW SN74HCT240PWR SN74HCT240PWT SNJ54HCT240J SNJ54HCT240W SNJ54HCT240J SNJ54HCT240W HT240 HCT240 HCT240 TOP-SIDE MARKING SN74HCT240N LCCC − FK Tube of 55 SNJ54HCT240FK SNJ54HCT240FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. Copyright  2003, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Y1 GND 2A1 1Y4 2A2 1 www.DataSheet4U.com SCLS174E − MARCH 1984 − REVISED AUGUST 2003 SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS FUNCTION TABLE (each buffer/driver) INPUTS OE L L H A H L X OUTPUT Y L H Z logic diagram (positive logic) 1OE 1 2OE 18 19 1A1 2 1Y1 2A1 11 9 2Y1 1A2 4 16 1Y2 2A2 13 7 2Y2 1A3 6 14 1Y3 2A3 15 5 2Y3 1A4 8 12 1Y4 2A4 17 3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS SCLS174E − MARCH 1984 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HCT240 MIN VCC VIH VIL VI VO ∆t/∆v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT240 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC† Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VO = VCC or 0, IOH = −20 µA IOH = −6 mA IOL = 20 µA IOL = 6 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 ±0.01 0.1 0.26 ±100 ±0.5 8 2.4 10 SN54HCT240 MIN 4.4 3.7 0.1 0.4 ±1000 ±10 160 3 10 MAX SN74HCT240 MIN 4.4 3.84 0.1 0.33 ±1000 ±5 80 2.9 10 V nA µA µA mA pF V MAX UNIT VI = VIH or VIL VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis tt FROM (INPUT) A OE OE TO (OUTPUT) Y Y Y Y VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 13 12 21 19 19 18 8 7 25 23 35 32 35 32 12 11 SN54HCT240 MIN MAX 37 33 53 48 53 48 18 16 SN74HCT240 MIN MAX 32 29 44 40 44 40 15 14 ns ns ns ns UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 www.DataSheet4U.com SCLS174E − MARCH 1984 − REVISED AUGUST 2003 SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tt FROM (INPUT) A OE TO (OUTPUT) Y Y Y VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 20 19 25 22 17 14 42 38 52 47 42 38 SN54HCT240 MIN MAX 63 56 79 71 63 57 SN74HCT240 MIN MAX 53 48 65 59 53 48 ns ns ns UNIT operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 40 UNIT pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS SCLS174E − MARCH 1984 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC S1 RL PARAMETER ten tPZH tPZL tPHZ tPLZ −− 50 pF or 150 pF 1 kΩ RL 1 kΩ CL 50 pF or 150 pF 50 pF S1 Open Closed Open Closed Open S2 Closed Open Closed Open Open From Output Under Test CL (see Note A) Test Point S2 tdis tpd or tt LOAD CIRCUIT Input 1.3 V 0.3 V 2.7 V 2.7 V 3V 1.3 V 0.3 V 0 V tf tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3V Input 1.3 V tPLH In-Phase Output 1.3 V 10% tPHL Out-ofPhase Output 90% 1.3 V 10% tf 90% tr tPLH 1.3 V 10% 90% tr VOH VOL 1.3 V 0V tPHL 90% VOH 1.3 V 10% V OL tf Output Control (Low-Level Enabling) 3V 1.3 V tPZL 1.3 V 0V tPLZ ≈VCC 1.3 V 10% tPHZ 1.3 V 90% VOH ≈0 V VOL Output Waveform 1 (See Note B) tPZH Output Waveform 2 (See Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 www.DataSheet4U.com www.ti.com PACKAGE OPTION ADDENDUM 28-Feb-2005 PACKAGING INFORMATION Orderable Device 85505012A 8550501RA JM38510/65753BRA SN54HCT240J SN74HCT240DW SN74HCT240DWR SN74HCT240N SN74HCT240NSR