QUADRUPLE 2-INPUT POSITIVE-AND GATES

www.DataSheet4U.com SN54HCT08, SN74HCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003 D D D Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC SN54HCT08 . . . J OR W PACKAGE SN74HCT08 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) D D D D Typical tpd = 13 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible SN54HCT08 . . . FK PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1A NC VCC 4B 1Y NC 2A NC 2B 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 4A NC 4Y NC 3B NC – No internal connection description/ordering information These devices contain four independent 2-input AND gates. They perform the Boolean function Y A • B or Y A B in positive logic. + +) ORDERING INFORMATION TA PDIP – N SOIC – D –40°C 85°C –40 C to 85 C SOP – NS SSOP – DB TSSOP – PW CDIP – J –55°C 125°C –55 C to 125 C CFP – W PACKAGE† Tube of 25 Tube of 50 Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Tube of 25 Tube of 150 ORDERABLE PART NUMBER SN74HCT08N SN74HCT08D SN74HCT08DR SN74HCT08DT SN74HCT08NSR SN74HCT08DBR SN74HCT08PW SN74HCT08PWR SN74HCT08PWT SNJ54HCT08J SNJ54HCT08W SNJ54HCT08J SNJ54HCT08W HT08 HCT08 HT08 HCT08 TOP-SIDE MARKING SN74HCT08N LCCC – FK Tube of 55 SNJ54HCT08FK SNJ54HCT08FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Y GND NC 3Y 3A 1 www.DataSheet4U.com SN54HCT08, SN74HCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y H L L SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003 logic diagram (positive logic) A B Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HCT08 MIN VCC VIH VIL VI VO ∆t/∆v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT08 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HCT08, SN74HCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II ICC ∆ICC† Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOH = –20 µA IOH = –4 mA IOL = 20 µA IOL = 4 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 0.1 0.26 ±100 2 2.4 10 SN54HCT08 MIN 4.4 3.7 0.1 0.4 ±1000 40 3 10 MAX SN74HCT08 MIN 4.4 3.84 0.1 0.33 ±1000 20 2.9 10 MAX UNIT V V nA µA mA pF IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd tt FROM (INPUT) A or B TO (OUTPUT) Y Y VCC 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 15 13 9 8 24 22 15 14 SN54HCT08 MIN MAX 35 32 22 20 SN74HCT08 MIN MAX 30 27 19 17 UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS No load TYP 20 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 www.DataSheet4U.com SN54HCT08, SN74HCT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output 3V Input 1.3 V tPLH 1.3 V 10% tPHL Out-of-Phase Output 90% 1.3 V 10% tf 90% tr Input 1.3 V 0.3 V 2.7 V 2.7 V 3V 1.3 V 0.3 V 0 V tf tPLH 1.3 V 10% 90% tr VOH VOL 1.3 V 0V tPHL 90% VOH 1.3 V 10% V OL tf SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003 LOAD CIRCUIT tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com www.ti.com PACKAGE OPTION ADDENDUM 6-Dec-2006 PACKAGING INFORMATION Orderable Device SN74HCT08D SN74HCT08DBLE SN74HCT08DBR SN74HCT08DBRE4 SN74HCT08DE4 SN74HCT08DR SN74HCT08DRE4 SN74HCT08DT SN74HCT08DTE4 SN74HCT08N SN74HCT08NE4 SN74HCT08NSR SN74HCT08NSRE4 SN74HCT08PW SN74HCT08PWE4 SN74HCT08PWLE SN74HCT08PWR SN74HCT08PWRE4 SN74HCT08PWT SN74HCT08PWTE4 (1) Status (1) ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SSOP SSOP SSOP SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP Package Drawing D DB DB DB D D D D D N N NS NS PW PW PW PW PW PW PW Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 50 Green (RoHS & no Sb/Br) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 50 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 250 250 Green (Ro