QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

www.DataSheet4U.com SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003 D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC Typical tpd = 10 ns SN54HC86 . . . J OR W PACKAGE SN74HC86 . . . D, N, NS, OR PW PACKAGE (TOP VIEW) D D D ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max True Logic SN54HC86 . . . FK PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1A NC VCC 4B 1Y NC 2A NC 2B 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 4A NC 4Y NC 3B NC – No internal connection description/ordering information These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function Y=A B or Y = AB + AB in positive logic. A common application is as a true / complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. ORDERING INFORMATION TA PDIP – N SOIC – D –40°C 85°C –40 C to 85 C SOP – NS TSSOP – PW CDIP – J –55°C 125°C –55 C to 125 C CFP – W LCCC – FK PACKAGE† Tube of 25 Tube of 50 Reel of 2500 Reel of 250 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC86N SN74HC86D SN74HC86DR SN74HC86DT SN74HC86NSR SN74HC86PW SN74HC86PWR SN74HC86PWT SNJ54HC86J SNJ54HC86W SNJ54HC86FK SNJ54HC86J SNJ54HC86W HC86 HC86 HC86 TOP-SIDE MARKING SN74HC86N SNJ54HC86FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Y GND NC 3Y 3A 1 www.DataSheet4U.com SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES FUNCTION TABLE (each gate) INPUTS A L L H H B L H L H OUTPUT Y L H H L SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003 exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. Exclusive OR =1 These are five equivalent exclusive-OR symbols valid for an ’HC86 gate in positive logic; negation may be shown at any two ports. Logic Identity Element = The output is active (low) if all inputs stand at the same logic level (i.e., A = B). Even-Parity Element 2k The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. Odd-Parity Element 2k + 1 The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC86 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v t/ v Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 2 V VCC = 4.5 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 0 0 NOM 5 MAX 6 SN74HC86 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 ns V V V V NOM 5 MAX 6 UNIT V VCC = 6 V 400 400 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 2V IOH = –20 µA A VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25°C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 0.1 0.1 0.1 0.26 0.26 ±100 2 10 SN54HC86 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 40 10 MAX SN74HC86 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 20 10 nA µA pF V V MAX UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 www.DataSheet4U.com SN54HC86, SN74HC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V tpd A or B Y 4.5 V 6V 2V tt Y 4.5 V 6V MIN TA = 25°C TYP MAX 40 12 10 28 8 6 100 20 17 75 15 13 SN54HC86 MIN MAX 150 30 25 110 22 19 SN74HC86 MIN MAX 125 25 21 95 19 16 ns ns UNIT SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003 operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS No load TYP 35 UNIT pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output Input VCC 50% tPLH 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr Input 50% 10% 90% 90% VCC 50% 10% 0 V tf tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL LOAD CIRCUIT tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com www.ti.com PACKAGE OPTION ADDENDUM 6-Oct-2005 PACKAGING INFORMATION Orderable Device 84046012A 8404601CA 8404601DA JM38510/65202BCA SN54HC86J SN74HC86D SN74HC86DE4 SN74HC86DR SN74HC86DRE4 SN74HC86DT SN74HC86DTE4 SN74HC86N SN74HC86NE4 SN74HC86NSR SN74HC86NSRE4 SN74HC86PW SN74HC86PWE4 SN74HC86PWLE SN74HC86PWR SN74HC86PWRE4 SN74HC86PWT SN74HC86PWTE4 SNJ54HC86FK SNJ54HC86J SNJ54HC86W (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type LCCC CDIP CFP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP LCCC CDIP CFP Package Drawing FK J W J J D D D D D D N N NS NS PW PW PW PW PW PW PW FK J W Pins Package Eco Plan (2) Qty 20 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 20 14 14 1 1 1 1 1 50 50 TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish Call TI Call TI Call TI Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI Call TI MSL Peak Temp (3) Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-NC-NC-NC Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UN