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SN54HC7002, SN74HC7002 QUADRUPLE POSITIVE NOR GATES WITH SCHMITT TRIGGER INPUTS
SCLS033F − MARCH 1984 − REVISED NOVEMBER 2004
D D D D D D D
Wide Operating Voltage Range of 2 V to 6 V Typical tpd = 14 ns Low Power Consumption, 20-µA Max ICC Low Input Current of 1 µA Max Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity
SN54HC7002 . . . J OR W PACKAGE SN74HC7002 . . . D, N, NS, OR PW PACKAGE (TOP VIEW)
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3B 3A 3Y
description/ordering information
In these devices, each circuit functions as a quadruple NOR gate. They perform the Boolean function Y = A • B or Y = A + B in positive logic. However, because of the Schmitt action, the inputs have different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
SN54HC7002 . . . FK PACKAGE (TOP VIEW)
1B 1A NC VCC 4B 1Y NC 2A NC 2B
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4A NC 4Y NC 3B
NC − No internal connection
ORDERING INFORMATION
TA PDIP − N PACKAGE† Tube of 25 Tube of 50 SOIC − D −40°C to 85°C SOP − NS Reel of 2500 Reel of 250 Reel of 2000 Tube of 90 TSSOP − PW CDIP − J −55 C 125°C −55°C to 125 C CFP − W LCCC - FK Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC7002N SN74HC7002D SN74HC7002DR SN74HC7002DT SN74HC7002NSR SN74HC7002PW SN74HC7002PWR SN74HC7002PWT SNJ54HC7002J SNJ54HC7002W SNJ54HC7002FK SNJ54HC7002J SNJ54HC7002W HC7002 HC7002 HC7002 TOP-SIDE MARKING SN74HC7002N
SNJ54HC7002FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright 2004, Texas Instruments Incorporated
• DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
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SCLS033F − MARCH 1984 − REVISED NOVEMBER 2004
SN54HC7002, SN74HC7002 QUADRUPLE POSITIVE NOR GATES WITH SCHMITT TRIGGER INPUTS
FUNCTION TABLE (each gate) INPUTS A H X L B X H L OUTPUT Y L L H
logic diagram (positive logic)
A Y B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC7002 MIN VCC VI VO TA Supply voltage Input voltage Output voltage Operating free-air temperature 2 0 0 −55 NOM 5 MAX 6 VCC VCC 125 SN74HC7002 MIN 2 0 0 −40 NOM 5 MAX 6 VCC VCC 85 UNIT V V V °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54HC7002, SN74HC7002 QUADRUPLE POSITIVE NOR GATES WITH SCHMITT TRIGGER INPUTS
SCLS033F − MARCH 1984 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V VT+ 4.5 V 6V 2V VT− 4.5 V 6V 2V VT+ − VT− 4.5 V 6V 2V IOH = −20 µA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 0.7 1.55 2.1 0.3 0.9 1.2 0.2 0.4 0.5 1.9 4.4 5.9 3.98 5.48 TA = 25°C TYP MAX 1.2 2.5 3.3 0.6 1.6 2 0.6 0.9 1.3 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 0.1 0.1 0.1 0.26 0.26 ±100 2 10 1.5 3.15 4.2 1 2.45 3.2 1.2 2.1 2.5 SN54HC7002 MIN 0.7 1.55 2.1 0.3 0.9 1.2 0.2 0.4 0.5 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 40 10 MAX 1.5 3.15 4.2 1 2.45 3.2 1.2 2.1 2.5 SN74HC7002 MIN 0.7 1.55 2.1 0.3 0.9 1.2 0.2 0.4 0.5 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 20 10 nA µA pF V V MAX 1.5 3.15 4.2 1 2.45 3.2 1.2 2.1 2.5 V V V UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V tpd A or B Y 4.5 V 6V 2V tt Any 4.5 V 6V TA = 25°C MIN TYP MAX 60 18 14 28 8 6 130 26 22 75 15 13 SN54HC7002 MIN MAX 195 39 33 110 22 19 SN74HC7002 MIN MAX 163 33 28 95 19 16 ns ns UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS No load TYP 20 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SCLS033F − MARCH 1984 − REVISED NOVEMBER 2004
SN54HC7002, SN74HC7002 QUADRUPLE POSITIVE NOR GATES WITH SCHMITT TRIGGER INPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point CL = 50 pF (see Note A) In-Phase Output Input VCC 50% tPLH 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr Input 50% 10% 90% 90% VCC 50% 10% 0 V tf tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL
LOAD CIRCUIT
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time, with one input transition per measurement. D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
6-Dec-2006
PACKAGING INFORMATION
Orderable Device SN74HC7002D SN74HC7002DE4 SN74HC7002DR SN74HC7002DRE4 SN74HC7002DT SN74HC7002DTE4 SN74HC7002N SN74HC7002NE4 SN74HC7002NSR SN74HC7002NSRE4 SN74HC7002PW SN74HC7002PWE4 SN74HC7002PWR SN74HC7002PWRE4 SN74HC7002PWT SN74HC7002PWTE4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Package Drawing D D D D D D N N NS NS PW PW PW PW PW PW
Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 50 50 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2000 Green (RoHS
