OCTAL BUS TRANSCEIVERS

www.DataSheet4U.com SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002 SN54HC645, SN74HC645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC SN54HC645 . . . J OR W PACKAGE SN74HC645 . . . DW, N, OR NS PACKAGE (TOP VIEW) D D D D Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max True Logic SN54HC645 . . . FK PACKAGE (TOP VIEW) A2 A1 DIR VCC DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 A3 A4 A5 A6 A7 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 OE B1 B2 B3 B4 B5 description/ordering information These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. ORDERING INFORMATION TA PDIP – N –40°C to 85°C 40°C SOIC – DW SOP – NS CDIP – J –55°C to 125°C CFP – W PACKAGE† Tube Tube Tape and reel Tape and reel Tube Tube ORDERABLE PART NUMBER SN74HC645N SN74HC645DW SN74HC645DWR SN74HC645NSR SNJ54HC645J SNJ54HC645W HC645 HC645 SNJ54HC645J SNJ54HC645W TOP-SIDE MARKING SN74HC645N LCCC – FK Tube SNJ54HC645FK SNJ54HC645FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002, Texas Instruments Incorporated On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A8 GND B8 B7 B6 1 www.DataSheet4U.com SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002 SN54HC645, SN74HC645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS logic diagram (positive logic) OE 19 DIR 1 A1 2 18 B1 To Seven Other Transceivers absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC645 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v TA Low level input Low-level in ut voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V Operating free-air temperature –55 VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 125 –40 0 0 NOM 5 MAX 6 SN74HC645 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 85 °C ns V V V V NOM 5 MAX 6 UNIT V High level input High-level in ut voltage In ut Input transition rise/fall time 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002 SN54HC645, SN74HC645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 2V IOH = –20 µA 20 VOH VI = VIH or VIL IOH = –6 mA IOH = –7.8 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 6 mA IOL = 7.8 mA II IOZ ICC Ci DIR or OE A or B DIR or OE VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25°C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 ±0.1 ±0.01 0.1 0.1 0.1 0.26 0.26 ±100 ±0.5 8 10 SN54HC645 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1000 ±10 160 10 MAX SN74HC645 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1000 ±5 80 10 nA µA µA pF V V MAX UNIT switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V tpd d A or B B or A 4.5 V 6V 2V ten OE A or B 4.5 V 6V 2V tdis OE A or B 4.5 V 6V 2V tt A or B 4.5 V 6V TA = 25°C MIN TYP MAX 40 15 12 125 23 20 74 25 21 20 8 6 105 21 18 230 46 39 200 40 34 60 12 10 SN54HC645 MIN MAX 160 32 27 340 68 58 300 60 51 90 18 15 SN74HC645 MIN MAX 130 26 22 290 58 49 250 50 43 75 15 13 ns ns ns ns UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 www.DataSheet4U.com SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002 SN54HC645, SN74HC645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V tpd d A or B B or A 4.5 V 6V 2V ten OE A or B 4.5 V 6V 2V tt A or B 4.5 V 6V MIN TA = 25°C TYP MAX 54 18 15 150 31 25 45 17 13 135 27 23 270 54 46 210 42 36 SN54HC645 MIN MAX 200 40 34 405 81 69 315 63 53 SN74HC645 MIN MAX 170 34 29 335 67 56 265 53 45 ns ns ns UNIT operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per transceiver TEST CONDITIONS No load TYP 40 UNIT pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4U.com SCLS304B – JANUARY 1996 – REVISED DECEMBER 2002 SN54HC645, SN74HC645 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION VCC PARAMETER Test Point S1 RL ten tPZH tPZL tPHZ tPLZ 1 kΩ RL 1 kΩ CL 50 pF or 150 pF 50 pF 50 pF or 150 pF S1 Open Closed Open Closed –– Open S2 Closed Open Closed Open Open From Output Under Test CL (see Note A) S2 tdis tpd or tt LOAD CIRCUIT VCC Input 50% tPLH In-Phase Output 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr VOH VOL 50% 0V tPHL 90% VOH 50% 10% V OL tf Output Control (Low-Level Enabling) tPZL Output Waveform 1 (See Note B) tPZH VCC 50% 50% 0V tPLZ ≈VCC 50% 10% tPHZ 50% 90% VOH ≈0 V ≈VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VCC 50% 10% 0 V tf Input 50% 10% 90% 90% Output Waveform 2 (See Note B) tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device SN54HC645J SN74HC645DW SN74HC645DWE4 SN74HC645DWR SN74HC645DWRE4 SN74HC645N SN74HC645NE4 SN74HC645NSR SN74HC645NSRE4 SNJ54HC645FK SNJ54HC645J (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP SOIC SOIC SOIC SOIC PDIP PDIP SO SO LCCC CDIP Package Drawing J DW DW DW DW N N NS NS FK J Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 20 20 20 1 25 25 TBD Green (RoHS & no Sb/Br) Green (RoHS