FLATLINKE RECEIVER

SN75LVDS86 FLATLINK™ RECEIVER SLLS268C – MARCH 1997 – REVISED MAY 1999 D D D D D D D D D D D D D 3:21 Data Channel Expansion at up to 163 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI 3 Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant SHTDN Input ESD Protection Exceeds 4 kV on Bus Pins Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz No External Components Required for PLL Open-Circuit Receiver Fail-Safe Design Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the DS90C562 DGG PACKAGE (TOP VIEW) description D17 D18 GND D19 D20 NC LVDSGND A0M A0P A1M A1P LVDSVCC LVDSGND A2M A2P CLKINM CLKINP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKOUT D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC D16 D15 D14 GND D13 VCC D12 D11 D10 GND D9 VCC D8 D7 D6 GND D5 D4 D3 VCC D2 D1 GND NC – Not Connected The SN75LVDS86 FlatLink receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT). The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design such that when the inputs are not connected to an LVDS driver, the receiver outputs go to a low-level. This occurs even when the line is differentially terminated at the receiver inputs. The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0_C to 70_C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75LVDS86 FLATLINK™ RECEIVER SLLS268C – MARCH 1997 – REVISED MAY 1999 functional block diagram Serial-In/ParallelOut Shift Register A0P A0M Serial In CLK A, B, ...G D0 D1 D2 D3 D4 D5 D6 Serial-In/ParallelOut Shift Register A1P A1M Serial In A, B, ...G CLK Serial-In/ParallelOut Shift Register Input Bus A2P A2M Serial In CLK D7 D8 D9 D10 D11 D12 D13 A, B, ...G Control Logic SHTDN D14 D15 D16 D17 D18 D19 D20 7× Clock/PLL CLKINP CLKINM CLK Clock In Clock Out CLKOUT 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS86 FLATLINK™ RECEIVER SLLS268C – MARCH 1997 – REVISED MAY 1999 CLKIN Previous Cycle A0 D0–1 D6 Current Cycle D3 Next Cycle D0 D6+1 D5 D4 D2 D1 A1 D7–1 D13 D12 D11 D10 D9 D8 D7 D13+1 A2 D14–1 D20 D19 D18 D17 D16 D15 D14 D20+1 CLKOUT D0 Dn – 1 Dn Figure 1. SN75LVDS86 Load and Shift Timing Sequences equivalent input and output schematic diagrams VCC VCC 300 kΩ 300 kΩ 5Ω AnP AnM VCC 7V 7V 7V 50 Ω SHTDN INPUT 7V 300 kΩ OUTPUT INPUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ÇÇÇ ÉÉ ÇÇÇ ÉÉ ÇÇ ÇÇ Dn + 1 D Output 3 ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ ÇÇ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ ÇÇ SN75LVDS86 FLATLINK™ RECEIVER SLLS268C – MARCH 1997 – REVISED MAY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Output voltage range, VO (Dxx terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range, VI (any terminal except SHTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input voltage range, VI (SHTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND unless otherwise noted. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING DGG 1316 mW 13.1 mW/°C 726 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. recommended operating conditions (see Figure 2) MIN Supply voltage, VCC High-level input voltage, VIH (SHTDN) Low-level input voltage, VIL (SHTDN) Differential input voltage, |VID| Common-mode input voltage, VIC (see Figure 2 and Figure 3) Operating free-air temperature, TA 0.1 |V ID 2 0 | 2.4 3 2 0.8 0.6 ID * |V2 | NOM 3.3 MAX 3.6 UNIT V V V V V °C VCC – 0.8 70 timing requirements MIN tc tsu1 Cycle time, input clock§ Setup time, input (see Figure 7) 14.7 600 600 NOM tc MAX 32.4 UNIT ns ps ps th1 Hold time, input (see Figure 7) § Parameter tc is defined as the mean duration of a minimum of 32 000 clock cycles. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS86 FLATLINK™ RECEIVER SLLS268C – MARCH 1997 – REVISED MAY 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ VIT– VOH VOL Positive-going differential input threshold voltage Negative-going differential input threshold voltage‡ High-level output voltage Low-level output voltage IOH = – 4 mA IOL = 4 mA Disabled, Enabled, AnM = 1.4 V, All inputs open AnP = 1 V, tc = 15.38 ns 58 –100 2.4 0.4 280 72 TEST CONDITIONS MIN TYP† MAX 100 UNIT mV mV V V µA mA ICC Quiescent current (average) Enabled, CL = 8 pF, Grayscale pattern (see Figure 4), tc = 15.38 ns Enabled, CL = 8 pF, Worst-case pattern (see Figure 5) tc = 15.38 ns VIH = VCC VIL = 0 0 ≤ VI ≤ 2.4 V VO = 0 or VCC 69 mA 94 ±20 ±20 ±20 ±10 mA µA µA µA µA IIH IIL II IOZ High-level input current (SHTDN) Low-level input current (SHTDN) Input current (LVDS input terminals A and CLKIN) High-impedance output current † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going input voltage threshold only. switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tsu2 th2 tRSKM td Set up time, D0 – D20 valid to CLKOUT↓ Hold time, CLKOUT↓ to D0 – D20 valid Receiver input skew margin§ (see Figure 7) Delay time, CLKIN↑ to CLKOUT↓ (see Figure 7) TEST CONDITIONS CL = 8 pF, , See Figure 6 tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps¶, tc = 15.38 ns (± 0.2%), CL = 8 pF tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns, See Figure 8 Cycle time C cle time, change in o tp t clock period# output tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns, See Figure 8 See Figure 9 See Figure 10 CL = 8 pF MIN 5 5 490 3.7 ± 80 ps ± 300 1 400 3 0.43 tc ms ns ns ns TYP† MAX UNIT ns ns ps ns ∆ tc(o) ( ) ten tdis tt tw Enable time, SHTDN↑ to Dn valid Disable time, SHTDN↓ to off state Transition time, output (10% to 90% tr or tf) Pulse duration, output clock † All typical values are at VCC = 3.3 V, TA = 25°C. tc § The parameter t(RSKM) is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by 14 ¶ |Input clock jitter| is the magnitude of the change in input clock period. # ∆ tc(o) is the change in the output clock period from one cycle to the next c