FLATLINK RECEIVER

www.DataSheet4U.com SN65LVDS86AQ, SN75LVDS86A FlatLink RECEIVER SLLS318C − NOVEMBER 1998 − REVISED JULY 2006 D 3:21 Data Channel Expansion at up to D D 178.5 Mbytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI Three Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.3-V Supply Tolerates 4-kV HBM ESD Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz No External Components Required for PLL Inputs Meet or Exceed the Standard Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the DS90C364 and SN75LVDS86 Improved Jitter Tolerance Available in Q-Temp Automotive High Reliability Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards D17 D18 GND D19 D20 NC LVDSGND A0M A0P A1M A1P LVDSVCC LVDSGND A2M A2P CLKINM CLKINP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKOUT D0 DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D D D D D D D D D D VCC D16 D15 D14 GND D13 VCC D12 D11 D10 GND D9 VCC D8 D7 D6 GND D5 D4 D3 VCC D2 D1 GND NC − Not connected description The SN65LVDS86AQ/SN75LVDS86A FlatLink receiver contains three serial-in 7-bit parallel-out shift registers and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a lower transfer rate. When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The ’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT). The ’LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2006, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65LVDS86AQ, SN75LVDS86A FlatLink RECEIVER SLLS318C − NOVEMBER 1998 − REVISED JULY 2006 The SN75LVDS86A is characterized for operation over ambient free-air temperatures of 0_C to 70_C. The SN65LVDS86AQ is characterized for operation over the full Automotive temperature range of −40°C to 125°C. functional block diagram Serial-In/ParallelOut Shift Register A0P A0M Serial In CLK A, B, ...G D0 D1 D2 D3 D4 D5 D6 Serial-In/ParallelOut Shift Register A1P A1M Serial In A, B, ...G CLK Serial-In/ParallelOut Shift Register A2P A2M Serial In CLK A, B, ...G D7 D8 D9 D10 D11 D12 D13 Control Logic SHTDN D14 D15 D16 D17 D18 D19 D20 Clock Generator CLKINP CLKINM CLK Clock In Clock Out CLKOUT Input Bus 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS86AQ, SN75LVDS86A FlatLink RECEIVER SLLS318C − NOVEMBER 1998 − REVISED JULY 2006 CLKIN Previous Cycle A0 D0−1 D6 Current Cycle D3 Next Cycle D0 D6+1 D5 D4 D2 D1 A1 D7−1 D13 D12 D11 D10 D9 D8 D7 D13+1 A2 D14−1 D20 D19 D18 D17 D16 D15 D14 D20+1 CLKOUT D0 Dn − 1 Dn Figure 1. SN65LVDS86AQ/SN75LVDS86A Load and Shift Timing Sequences equivalent input and output schematic diagrams VCC VCC 300 kΩ 300 kΩ 5Ω 100 Ω AnP 100 Ω AnM 7V 7V 7V VCC INPUT 50 Ω OUTPUT SHTDN 7V INPUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ÇÇ ÇÇ ÇÇÇ ÇÇÇ Dn + 1 D Output 3 ÉÉ ÉÉ ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ ÇÇ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÇÇ ÇÇ ÇÇ ÇÇ SN65LVDS86AQ, SN75LVDS86A FlatLink RECEIVER SLLS318C − NOVEMBER 1998 − REVISED JULY 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Voltage range at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Electrostatic discharge (see Note 2): All pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 KV All pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40_C to 150_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C Lead temperature 1,6 mm (1/16 in) from case for 10 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminals unless otherwise noted. 2. This rating is measured using MIL-STD-883C Method, 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 125°C POWER RATING DGG 1637 mW 13.1 mW/°C 1048 mW 327 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. recommended operating conditions (see Figure 2) MIN Supply voltage, VCC High-level input voltage, VIH (SHTDN) Low-level input voltage, VIL (SHTDN) Magnitude differential input voltage, |VID| Common-mode input voltage, VIC SN75LVDS86A Operating free-air temperature, TA SN65LVDS86AQ 0.1 |V ID 2 0 −40 | 3 2 0.8 0.6 2.4 * |V ID 2 | NOM 3.3 MAX 3.6 UNIT V V V V V °C 70 125 timing requirements MIN Cycle time, input clock, tc§ § Parameter tc is defined as the mean duration of a minimum of 32 000 clock cycles. 14.7 NOM tc MAX 32.4 UNIT ns 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDS86AQ, SN75LVDS86A FlatLink RECEIVER SLLS318C − NOVEMBER 1998 − REVISED JULY 2006 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ VIT− VOH VOL Positive-going differential input threshold voltage Negative-going differential input threshold voltage‡ High-level output voltage Low-level output voltage IOH = − 4 mA IOL = 4 mA Disabled, Enabled, AnM = 1.4 V, ICC Quiescent current (average) All inputs to GND AnP = 1 V, tc = 15.38 ns 33 −100 2.4 0.4 280 40 TEST CONDITIONS MIN TYP† MAX 100 UNIT mV mV V V µA Enabled, CL = 8 pF, Grayscale pattern (see Figure 3), tc = 15.38 ns Enabled, CL = 8 pF, Worst-case pattern (see Figure 4) tc = 15.38 ns VIH = VCC SN75LVDS86A VIL = 0 0 ≤ VI ≤ 2.4 V VO = 0 or VCC SN65LVDS86AQ 43 mA 68 ±20 ±20 ±25 ±20 ±10 µA µA A µA µA IIH IIL II IOZ High-level input current (SHTDN) Low-level input current (SHTDN) Input current A inputs High-impedance output current † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going input voltage threshold only. switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tsu th Setup time, D0–D20 to CLKOUT↓ Data hold time, CLKOUT↓ to D0–D20 CL = 8 pF, See Figure 5 tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps¶, VCC = 3.3 V, tc = 15.38 ns (± 0.2%), TA = 25°C See Figure 7 See Figure 8 CL = 8 pF CL = 8 pF TEST CONDITIONS MIN 5 5 550 3 700 5 1 400 3 1.5 7 TYP† MAX UNIT ns ns ps ns ms ns ns ns t(RSKM) Receiver input skew margin§ (see Figure 7) td ten tdis tt tt Delay time, CLKIN↑ to CLKOUT↓ (see Figure 7) Enable time, SHTDN to phase lock Disable time, SHTDN to off state Transition time, output (10% to 90% tr or tf) (data only) Transition time, output (10% to 90% tr or tf) (clock only) tw Pulse duration, output clock 0.50 tc ns † All typical values are at VCC = 3.3 V, TA = 25°C. § The parameter t(RSKM) is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter at clock periods other than 15.38 ns can be calculated from tRSKM = tc/14 – 550 ps. ¶ |Input clock jitter| is the magnitude of the change in input clock period. POST OFFICE BOX