DUAL 4-INPIT POSITIVE-AND GATES

www.DataSheet4U.com SN54LV21A, SN74LV21A DUAL 4 INPUT POSITIVE AND GATES SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54LV21A . . . J OR W PACKAGE SN74LV21A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 1A 1B NC 1C 1D 1Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 2D 2C NC 2B 2A 2Y SN54LV21A . . . FK PACKAGE (TOP VIEW) description/ordering information These dual 4-input positive-AND gates are designed for 2-V to 5.5-V VCC operation. The ’LV21A devices perform the Boolean function Y + A • B • C • D or Y + A ) B ) C ) D in positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. ORDERING INFORMATION TA SOIC − D SOP − NS SSOP − DB −40°C to 85°C TSSOP − PW TVSOP − DGV CDIP − J −55 C 125°C −55°C to 125 C CFP − W PACKAGE† Tube of 50 Reel of 2500 Reel of 2000 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Reel of 2000 Tube of 25 Tube of 150 1B 1A NC VCC 2D NC NC 1C NC 1D 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 2C NC NC NC 2B NC − No internal connection ORDERABLE PART NUMBER SN74LV21AD SN74LV21ADR SN74LV21ANSR SN74LV21ADBR SN74LV21APW SN74LV21APWR SN74LV21APWT SN74LV21ADGVR SNJ54LV21AJ SNJ54LV21AW LCCC − FK Tube of 55 SNJ54LV21AFK SNJ54LV21AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Copyright  2004, Texas Instruments Incorporated • DALLAS, TEXAS 75265 1Y GND NC 2Y 2A TOP-SIDE MARKING LV21A 74LV21A LV21A LV21A LV21A SNJ54LV21AJ SNJ54LV21AW 1 SN54LV21A, SN74LV21A DUAL 4 INPUT POSITIVE AND GATES SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004 FUNCTION TABLE (each gate) INPUTS A H L X X X B H X L X X C H X X L X D H X X X L OUTPUT Y H L L L L logic diagram (positive logic) 1A 1B 1C 1D 1 2 4 5 6 1Y 2A 2B 2C 2D 9 10 12 13 8 2Y Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV21A, SN74LV21A DUAL 4 INPUT POSITIVE AND GATES SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004 recommended operating conditions (see Note 4) SN54LV21A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC −50 −2 −6 −12 50 2 6 12 200 100 20 0 0 MAX 5.5 SN74LV21A MIN 2 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC −50 −2 −6 −12 50 2 6 12 200 100 20 ns/V mA µA mA V V MAX 5.5 UNIT V VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage Output voltage V V µA IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV21A PARAMETER TEST CONDITIONS IOH = −50 µA IOH = −2 mA IOH = −6 mA IOH = −12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 to 5.5 V 5.5 V 0 3.3 V 1.9 MIN VCC−0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 20 5 1.9 TYP MAX SN74LV21A MIN VCC−0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 ±1 20 5 µA µA µA pF V V TYP MAX UNIT VOH VOL II ICC Ioff Ci PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV21A, SN74LV21A DUAL 4 INPUT POSITIVE AND GATES SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd FROM (INPUT) A, B, C, or D A, B, C, or D TO (OUTPUT) Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN TA = 25°C TYP MAX 7* 9.2 12* 15.7 SN54LV21A MIN 1* 1 MAX 14* 19 SN74LV21A MIN 1 1 MAX 14 19 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd FROM (INPUT) A, B, C, or D A, B, C, or D TO (OUTPUT) Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF TA = 25°C MIN TYP MAX 5.1* 6.6 7* 10.5 SN54LV21A MIN 1* 1 MAX 8.5* 12 SN74LV21A MIN 1 1 MAX 8.5 12 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd FROM (INPUT) A, B, C, or D A, B, C, or D TO (OUTPUT) Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN TA = 25°C TYP MAX 3.8* 4.9 5* 7 SN54LV21A MIN 1* 1 MAX 6* 8 SN74LV21A MIN 1 1 MAX 6 8 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV21A PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2.31 0.99 MIN TYP 0.2 0 3.2 MAX 0.8 −0.8 UNIT V V V V V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC 3.3 V 5V TYP 17.4 20.2 pF UNIT PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characterist