12-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR

www.DataSheet4U.com SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω Latch-Up Testing Done to JEDEC Standard JESD 78 ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) VREF 1AO 2AO 5A 6A EN1 11BI 11A 9BI 3AO 4AO 10AI1 10AI2 GND PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC 1BI 2BI 7BO1 7BO2 EN2 11BO 5BI 6BI 3BI 4BI 10BO1 10BO2 9AO DESCRIPTION/ORDERING INFORMATION The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon™ processor GTL–/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications. PIN DESCRIPTION PIN NO. 1 2–6, 8, 10–13, 15, 23 7, 9, 16, 17–22, 24–27 14 28 SYMBOL VREF ENn nAn nBn GND VCC NAME AND FUNCTION GTL reference voltage Data and enable inputs/outputs (LVTTL) on all inputs and pin 15 output. Remaining outputs are open drain. Data inputs/outputs (GTL–/GTL/GTL+) Ground (0 V) Positive supply voltage ORDERING INFORMATION TA –40°C to 85°C (1) TSSOP – PW PACKAGE (1) Tube Tape and reel ORDERABLE PART NUMBER SN74GTL2107PW SN74GTL2107PWR TOP-SIDE MARKING GK2107 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Xeon is a trademark of Intel Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR SCLS699 – JULY 2006 www.ti.com FUNCTION TABLES (1) INPUTS EN1 H H L (1) 1BI/2BI L H X OUTPUT 1AO/2AO (OPEN DRAIN) L H H H = High voltage level, L = Low voltage level INPUTS EN2 H H L INPUT 9BI L H INPUTS 10AI1/10AI2 L L H H INPUTS EN2 H H H L L L L 5BI/6BI L H H H H L L 9BI L H L H INPUT/OUTPUT 5A/6A (OPEN DRAIN) L L (2) H L (2) H H L (2) 3BI/4BI L H X OUTPUT 9AO L H OUTPUT 10BO1/10BO2 L L L H OUTPUT 3AO/4AO (OPEN DRAIN) L H H OUTPUT 7BO1/7BO2 H (1) L H L H H H (1) (2) The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (where 5BI/6BI goes from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. Open-drain input/output terminal is driven to a logic-low state by an external driver. INPUT 11BI L L H INPUT/OUTPUT 11A (OPEN DRAIN) H L (1) L OUTPUT 11BO L H H (1) Open-drain input/output terminal is driven to a logic-low state by an external driver. 2 Submit Documentation Feedback www.ti.com SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR SCLS699 – JULY 2006 LOGIC SYMBOL SN74GTL2107 GTL V REF 1 27 1AO LVTTL OD OUTPUTS 2AO 3 2 26 1BI GTL INPUTS 2BI 5A (OPEN DRAIN) LVTTL I/O 6A (OPEN DRAIN) 4 25 7BO1 GTL OUTPUTS 7BO2 5 24 LVTTL INPUT EN1 GTL INPUT 11BI 6 7 23 22 DELAY1 21 EN2 LVTTL INPUT 11BO GTL OUTPUT LVTTL I/O 11A (OPEN DRAIN) 8 9 5BI GTL INPUT 9BI DELAY1 20 6BI GTL INPUTS 3BI 19 3AO LVTTL OD OUTPUTS 4AO 11 10 18 4BI 17 10AI1 LVTTL INPUTS 10AI2 13 12 16 10BO1 GTL OUTPUTS 10BO2 15 9AO LVTTL OUTPUT (1) The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (where 5BI/6BI go from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. Submit Documentation Feedback 3 SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR SCLS699 – JULY 2006 www.ti.com Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN VCC VI VO IIK IOK Supply voltage range Input voltage range (3) Output voltage range (output in OFF or HIGH state) (3) Input diode current Output diode current Current into any output in the LOW state Current into any output in the HIGH state θJA Tstg (1) (2) (3) (4) Package thermal impedance (4) Storage temperature range –60 A port (LVTTL) B port (GTL) A port B port VI < 0 VO < 0 A port B port A port –0.5 –0.5 –0.5 –0.5 –0.5 MAX 4.6 4.6 4.6 4.6 4.6 –50 –50 32 30 –32 62 150 UNIT V V V mA mA mA mA °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are referenced to GND (ground = 0 V). The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit, in conjunction with its thermal environment, can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. Recommended Operating Conditions MIN VCC VTT Supply voltage GTL– Termination voltage GTL GTL+ Overall VREF Reference voltage GTL– GTL GTL+ VI VIH VIL IOH IOL TA Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature A port B port A port B port A port B port A port A port B port –40 3 0.85 1.14 1.35 0.5 0.5 0.76 0.87 0 0 2 VREF + 50 mV 0.8 VREF – 50 mV –16 16 15 85 NOM 3.3 0.9 1.2 1.5 2/3 VTT 0.6 0.8 1 3.3 VTT MAX 3.6 0.95 1.26 1.65 1.8 0.63 0.84 1.1 3.6 3.6 V V V mA mA °C V V UNIT V 4 Submit Documentation Feedback www.ti.com SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR SCLS699 – JULY 2006 Electrical Characteristics over recommended operating conditions PARAMETER VOH (2) VOL (2) A port A port B port A port B port ICC ∆ICC (3) CIO (1) (2) (3) A or B port A port or control inputs A port B port TEST CONDITIONS VCC = 3 V to 3.6 V, IOH = –100 µA VCC = 3 V, IOH = –16 mA VCC = 3 V, IOL = 16 mA VCC = 3 V, IOL = 15 mA VCC = 3.6 V, VI = VCC VCC = 3.6, VI = 0 V VCC = 3.6 V, VI = VTT or GND VCC = 3.6 V, VI = VCC or GND, IO = 0 VCC = 3.6 V, VI = VCC – 0.6 V VO = 3 V or 0 VO = VTT or 0 5 4 –40°C to 85°C MIN VCC – 0.2 2.1 0.8 0.4 ±1 ±1 ±1 12 500 mA µA pF µA TYP (1) MAX UNIT V V II All typical values are at VCC = 3.3 V, TA = 25°C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. This is the increase in supply current for each input that is at the specified LVTTL voltage, rather than VCC or GND. Switching Characteristics over recommended operating free-air temperature range GTL– PARAMETER WAVEFORM VCC = 3.3 V ± 0.3 V VREF = 0.6 V MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL (2) tPLH tPHL tPLZ tPZL tPLZ tPZL tPLZ tPZL tPLZ tPZL (1) (2) An to Bn 9BI to 9AO 9BI to 10BOn 11BI to 11BO Bn to Bn ENn to An Bn to An (I/O) Bn to An EN2 to An (I/O) 1 2 3 3 3 5 4 4 5 2 2 2 2 2 2 2 2 4 120 1 1 2 2 2 2 1 1 TYP (1) 4 5.5 5.5 5.5 6 6 8 14 7 205 3 3 5 5 5 5 3 3 MAX 8 10 10 10 11 11 13 21 11 350 7 7 10 10 10 10 7 7 GTL VCC = 3.3 V ± 0.3 V VREF = 0.8 V MIN 2 2 2 2 2 2 2 2 4 120 1 1 2 2 2 2 1 1 TYP (1) 4 5.5 5.5 5.5 6 6 8 14 7 205 3 3 5 5 5 5 3 3 MAX 8 10 10 10 11 11 13 21 11 350 7 7 10 10 10 10 7 7 GTL+ VCC = 3.3 V ± 0.3 V VREF = 1 V MIN 2 2 2 2 2 2 2 2 4 120 1 1 2 2 2 2 1 1 TYP (1) MAX 4 5.5 5.5 5.5 6 6 8 14 7 205 3 3 5 5 5 5 3 3 8 10 10 10 11 11 13 21 11 350 7 7 10 10 10 10 7 7 ns ns ns ns ns ns ns ns ns UNIT All typical values are measured at VCC = 3.3 V and TA = 25°C. Includes –7.6-ns RC rise time of test-load pullup on 11 A, 1.5-kΩ pullup, and 21-pF load on 11 A has approximately 23-ns RC rise time. Submit Documentation Feedback 5 SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR SCLS699 – JULY 2006 www.ti.com PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V, VREF = 0.8 V for GTL and VTT = 1.5 V, VREF = 1 V for GTL+ 2 y VCC From Output Under Test CL = 50 pF (see Note A) 500 Ω S1 Open GND 500 Ω TEST tPLH/tPHL tPLZ/tPZL S1 Open 2 y VCC VTT 50 Ω From Output Under Test CL = 30 pF (see Note A) Test Point LOAD CIRCUIT FOR A OUTPUTS Input (see Note B) 3V 1.5 V 1.5 V 0V tPLH Output tPHL VTT VREF VOLTAGE WAVEFORM 1 PROPAGATION DELAY TIMES (A port to B port)† VREF VOL Output tPLH Input (see Note B) LOAD CIRCUIT FOR B OUTPUTS VTT VREF VREF 0V tPHL VOH 1.5 V VOLTAGE WAVEFORM 2 PROPAGATION DELAY TIMES (B port to A port)† VTT VREF VREF 0V tPLH tPHL VTT 1.5 V VOL Input (see Note B) Output VREF VOLTAGE WAVEFORM 3 PROPAGATION DELAY TIMES (B port to B port)† VTT VREF VOL Input (see Note B) VREF VREF 0V Input (see Note B) 3V 1.5 V 1.5 V 0V VCC tPZL tPLZ tPZL Output S1 at 2 y VCC tPLZ VCC 1.5 V VOL + 0.3 V VOL Output S1 at 2 y VCC 1.5 V VOL + 0.3 V VOL VOLTAGE WAVEFORM 4 PROPAGATION DELAY TIMES (B port to A (I/O) port)† † VOLTAGE WAVEFORM 5 ENABLE AND DISABLE TIMES (EN2 to A(I/O) and ENn to An port)† All control inputs are LVTTL levels. NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 Submit Documentation Feedback www.ti.com SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR SCLS699 – JULY 2006