8-BIT FET BUS SWITCH 5-V BUS SWITCH

www.DataSheet4U.com SN74CBT3345C 8 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION SCDS129A − SEPTEMBER 2003 − REVISED OCTOBER 2003 D Undershoot Protection for Off-Isolation on D D D D D D D A and B Ports Up To −2 V Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) D Control Inputs Can Be Driven by TTL or D D D 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: USB Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating D RGY PACKAGE (TOP VIEW) OE A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 1 20 19 OE 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 10 11 description/ordering information The SN74CBT3345C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3345C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBT3345C is organized as an 8-bit bus switch with two output-enable (OE, OE) inputs. When OE is high or OE is low, the bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is low and OE is high, the bus switch is OFF and the high-impedance state exists between the A and B ports. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GND B8 VCC OE 1 SCDS129A − SEPTEMBER 2003 − REVISED OCTOBER 2003 SN74CBT3345C 8 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. ORDERING INFORMATION TA QFN − RGY SOIC − DW SSOP − DB SSOP (QSOP) − DBQ TSSOP − PW PACKAGE† Tape and reel Tube Tape and reel Tube −40 C 85°C −40°C to 85 C Tape and reel Tape and reel Tube Tape and reel ORDERABLE PART NUMBER SN74CBT3345CRGYR SN74CBT3345CDW SN74CBT3345CDWR SN74CBT3345CDB SN74CBT3345CDBR SN74CBT3345CDBQR SN74CBT3345CPW SN74CBT3345CPWR CU345C CU345C CBT3345C CBT3345C TOP-SIDE MARKING CU345C TVSOP − DGV Tape and reel SN74CBT3345CDGVR CU345C † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OE H X L OE X L H INPUT/OUTPUT A B B Z FUNCTION A port = B port A port = B port Disconnect logic diagram (positive logic) 2 A1 SW 9 SW 1 OE OE 19 11 18 B1 A8 B8 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT3345C 8 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION SCDS129A − SEPTEMBER 2003 − REVISED OCTOBER 2003 simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† † EN is the internal enable signal applied to the switch. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W (see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 5): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 7) MIN VCC VIH VIL VI/O Supply voltage High-level control input voltage Low-level control input voltage Data input/output voltage 4 2 0 0 MAX 5.5 5.5 0.8 5.5 UNIT V V V V TA Operating free-air temperature −40 85 °C NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCDS129A − SEPTEMBER 2003 − REVISED OCTOBER 2003 SN74CBT3345C 8 BIT FET BUS SWITCH 5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VIKU IIN IOZ‡ Ioff ICC ∆ICC§ Cin Cio(OFF) Cio(ON) Control inputs Control inputs Control inputs Data inputs Control inputs VCC = 4.5 V, VCC = 5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VIN = 3 V or 0 VI/O = 3 V or 0, VI/O = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ron¶ VCC = 4.5 V TEST CONDITIONS IIN = −18 mA 0 mA > II ≥ −50 mA, VIN = VCC or GND, VIN = VCC or GND VO = 0 to 5.5 V, VI = 0, VO = 0 to 5.5 V, II/O = 0, VIN = VCC or GND, One input at 3.4 V, Switch OFF, Switch ON, VI = 2.4 V, VI = 0 MIN TYP† MAX −1.8 Switch OFF −2 ±1 Switch OFF, VIN = VCC or GND VI = 0 Switch ON or OFF Other inputs at VCC or GND 4 VIN = VCC or GND VIN = VCC or GND IO = −15 mA IO = 64 mA IO = 30 mA 5.5 14 8 3 3 12 6 6 Ω ±10 10 3 2.5 UNIT V V µA µA µA µA mA pF pF pF VI = 2.4 V, IO = −15 mA 5 10 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tpd# ten FROM (INPUT) A or B OE or OE TO (OUTPUT) B or A A or B VCC = 4 V MIN MAX 0.24 5.3 1.5 VCC = 5 V ± 0.5 V MIN MAX 0.15 4.9 ns ns UNIT tdis A or B 5.8 1.5 5.7 ns OE or OE # The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltag