SN74CB3Q3305 DUAL FET BUS SWITCH 2.5 V/3.3 V LOW VOLTAGE HIGH BANDWIDTH BUS SWITCH
SCDS141A − OCTOBER 2003 − REVISED NOVEMBER 2003
D High-Bandwidth Data Path D D D D D D
(Up To 500 MHz†) 5-V Tolerant I/Os with Device Powered-Up or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast Switching Frequency (fOE = 20 MHz Max)
D Data and Control Inputs Provide D D D D D D D
Undershoot Clamp Diodes Low Power Consumption (ICC = 0.25 mA Typical) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating
† For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008.
D
PW PACKAGE (TOP VIEW)
1OE 1A 1B GND
1 2 3 4
8 7 6 5
VCC 2OE 2B 2A
description/ordering information
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. ORDERING INFORMATION
TA −40°C to 85°C PACKAGE‡ Tube TSSOP − PW Tape and reel ORDERABLE PART NUMBER SN74CB3Q3305PW SN74CB3Q3305PWR BU305 TOP-SIDE MARKING
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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SCDS141A − OCTOBER 2003 − REVISED NOVEMBER 2003
SN74CB3Q3305 DUAL FET BUS SWITCH 2.5 V/3.3 V LOW VOLTAGE HIGH BANDWIDTH BUS SWITCH
description/ordering information (continued)
The SN74CB3Q3305 is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 1-bit bus switches, or as one 2-bit bus switch. When OE is high, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is low, the associated 1-bit bus switch is OFF and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
FUNCTION TABLE (each bus switch) INPUT OE H L INPUT/OUTPUT A B Z FUNCTION A port = B port Disconnect
logic diagram (positive logic)
2 1A 1OE 1 SW 3 1B
5 2A 7 2OE SW
6 2B
simplified schematic, each FET switch (SW)
A VCC B
Charge Pump
EN† † EN is the internal enable signal applied to the switch.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CB3Q3305 DUAL FET BUS SWITCH 2.5 V/3.3 V LOW VOLTAGE HIGH BANDWIDTH BUS SWITCH
SCDS141A − OCTOBER 2003 − REVISED NOVEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±64 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN VCC VIH VIL VI/O TA Supply voltage High-level control input voltage Low-level control input voltage Data input/output voltage Operating free-air temperature VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0 0 0 −40 MAX 3.6 5.5 5.5 0.7 0.8 5.5 85 V V °C V UNIT V
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCDS141A − OCTOBER 2003 − REVISED NOVEMBER 2003
SN74CB3Q3305 DUAL FET BUS SWITCH 2.5 V/3.3 V LOW VOLTAGE HIGH BANDWIDTH BUS SWITCH
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK IIN IOZ‡ Ioff ICC ∆ICC§ ICCD¶ Cin Control inputs Per control input Control inputs Control inputs VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 V, VCC = 0, VCC = 3.6 V, TEST CONDITIONS II = −18 mA VIN = 0 to 5.5 V VO = 0 to 5.5 V, VI = 0, VO = 0 to 5.5 V, II/O = 0, Switch ON or OFF, Switch OFF, VIN = VCC or GND VI = 0 VIN = VCC or GND Other inputs at VCC or GND 0.040 2.5 3.5 8 3 3.5 3 3.5 0.25 MIN TYP† MAX −1.8 ±1 ±1 1 0.7 25 0.045 3.5 5 10.5 8 9 6 8 Ω UNIT V µA µA µA mA µA mA/ MHz pF pF pF
VCC = 3.6 V, One input at 3 V, VCC = 3.6 V, A and B ports open, Control input switching at 50% duty cycle VCC = 3.3 V, VCC = 3.3 V, VCC = 3.3 V, VCC = 2.3 V, TYP at VCC = 2.5 V VCC = 3 V
Cio(OFF) Cio(ON)
VIN = 5.5 V, 3.3 V, or 0 Switch OFF, VI/O = 5.5 V, 3.3 V, or 0 VIN = VCC or GND, Switch ON, VIN = VCC or GND, VI = 0, VI = 1.7 V, VI = 0, VI = 2.4 V, VI/O = 5.5 V, 3.3 V, or 0 IO = 30 mA IO = −15 mA IO = 30 mA IO = −15 mA
ron#
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2). # Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER fOE|| tpdk ten FROM (INPUT) OE A or B OE TO (OUTPUT) A or B B or A A or B 1 VCC = 2.5 V ± 0.2 V MIN MAX 10 0.09 5 1 VCC = 3.3 V ± 0.3 V MIN MAX 20 0.15 4.5 MHz ns ns UNIT
tdis A or B 1 4.5 1 5 ns OE || Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0) k The propagation delay is the calculated RC time constant of the typical ON-state resista
