QUADRUPLE 2-INPUT POSITIVE-NAND GATE

SN74AUC00 QUADRUPLE 2 INPUT POSITIVE NAND GATE SCES510 − NOVEMBER 2003 D Optimized for 1.8-V Operation and Is 3.6-V D D D D D D D I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 2 ns at 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) RGY PACKAGE (TOP VIEW) 1 14 13 4B 12 4A 11 4Y 10 3B 9 3A 1B 1Y 2A 2B 2Y 2 3 4 5 6 7 8 description/ordering information This quadruple 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC00 devices perform the Boolean function Y = A • B or Y = A + B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. www.DataSheet4U.com ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER GND TOP-SIDE MARKING −40°C to 85°C QFN − RGY Tape and reel SN74AUC00RGYR MS00 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y L H H logic diagram, each gate (positive logic) A B Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3Y VCC 1A 1 SN74AUC00 QUADRUPLE 2 INPUT POSITIVE NAND GATE SCES510 − NOVEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 3) MIN VCC VIH Supply voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 0.8 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 0.8 V VCC = 1.1 V IOH High-level output current VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 0.8 V IOL Low-level output current VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V ∆t/∆v Input transition rise or fall rate VCC = 0.8 V to 1.65 V† VCC = 1.65 V to 2.3 V‡ VCC = 2.3 V to 2.7 V‡ VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V 0 0 0.8 VCC 0.65 × VCC 1.7 0 0.35 × VCC 0.7 3.6 VCC −0.7 −3 −5 −8 −9 0.7 3 5 8 9 20 20 20 ns/V mA mA V V V MAX 2.7 UNIT V High-level input voltage V TA Operating free-air temperature −40 85 °C † The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1). ‡ The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1). NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUC00 QUADRUPLE 2 INPUT POSITIVE NAND GATE SCES510 − NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = −100 µA IOH = −0.7 mA VOH IOH = −3 mA IOH = −5 mA IOH = −8 mA IOH = −9 mA IOL = 100 µA IOL = 0.7 mA VOL IOL = 3 mA IOL = 5 mA IOL = 8 mA IOL = 9 mA II Ioff ICC Ci A or B inputs VI = VCC or GND VI or VO = 2.7 V VI = VCC or GND, VI = VCC or GND IO = 0 TEST CONDITIONS VCC 0.8 V to 2.7 V 0.8 V 1.1 V 1.4 V 1.65 V 2.3 V 0.8 V to 2.7 V 0.8 V 1.1 V 1.4 V 1.65 V 2.3 V 0 to 2.7 V 0 0.8 V to 2.7 V 2.5 V 2 0.25 0.3 0.4 0.45 0.6 ±5 ±10 10 µA µA µA pF V 0.8 1 1.2 1.8 0.2 V MIN VCC−0.1 0.55 TYP† MAX UNIT † All typical values are at TA = 25°C. switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A or B TO (OUTPUT) Y VCC = 0.8 V TYP 4.7 VCC = 1.2 V ± 0.1 V MIN 0.6 MAX 3.6 VCC = 1.5 V ± 0.1 V MIN 0.5 MAX 2.6 VCC = 1.8 V ± 0.15 V MIN 0.4 TYP 0.9 MAX 2 VCC = 2.5 V ± 0.2 V MIN 0.4 MAX 1.1 ns UNIT switching characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A or B TO (OUTPUT) Y VCC = 1.8 V ± 0.15 V MIN 0.6 TYP 1.5 MAX 2.4 VCC = 2.5 V ± 0.2 V MIN 0.5 MAX 2 ns UNIT operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 0.8 V TYP 13 VCC = 1.2 V TYP 13 VCC = 1.5 V TYP 13 VCC = 1.8 V TYP 13 VCC = 2.5 V TYP 16 UNIT pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AUC00 QUADRUPLE 2 INPUT POSITIVE NAND GATE SCES510 − NOVEMBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC From Output Under Test CL (see Note A) RL VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V RL S1 Open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH CL 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF S1 Open 2 × VCC GND RL 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω LOAD CIRCUIT V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input tw VCC Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCC Input tPLH Output tPHL VCC/2 VCC/2 VCC/2 VCC/2 0V tPHL VOH VCC/2 VOL tPLH VOH Output VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VCC/2 tPZH VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 VCC/2 0V tPLZ VCC VOL + V∆ tPHZ VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL Data Input tsu VCC/2 th VCC VCC/2 0V VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support thi