QUADRUPLE 2-INPUT POSITIVE-AND GATE

SN74ALVC08 Q1 QUADRUPLE 2 INPUT POSITIVE AND GATE SCES491B − SEPTEMBER 2003 − REVISED MAY 2004 D Qualification in Accordance With D D D D D D AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Operates From 1.65 V to 3.6 V Max tpd of 2.9 ns at 3.3 V ±24-mA Output Drive at 3.3 V D Latch-Up Performance Exceeds 250 mA Per JESD 17 D OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y † Contact factory for details. Q100 qualification data available on request. description/ordering information The SN74ALVC08 quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation. The device performs the Boolean function Y + A • B or Y + A ) B in positive logic. ORDERING INFORMATION TA SOIC − D −40°C to 85°C TSSOP − PW PACKAGE‡ Tape and reel Tape and reel ORDERABLE PART NUMBER SN74ALVC08IDRQ1 SN74ALVC08IPWRQ1 TOP-SIDE MARKING ALVC08I VA08I ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y H L L logic diagram, each gate (positive logic) A B Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2004, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC08 Q1 QUADRUPLE 2 INPUT POSITIVE AND GATE SCES491B − SEPTEMBER 2003 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) MIN VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 1.65 0.65 × VCC 1.7 2 0.35 × VCC 0.7 0.8 3.6 VCC −4 −12 −12 −24 4 12 12 24 5 ns/V mA mA V V V V MAX 3.6 UNIT V High-level input voltage VIL VI VO Low-level input voltage Input voltage Output voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC08 Q1 QUADRUPLE 2 INPUT POSITIVE AND GATE SCES491B − SEPTEMBER 2003 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = −100 µA IOH = −4 mA IOH = −6 mA VOH IOH = −12 mA IOH = −24 mA IOL = 100 µA IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA VI = VCC or GND VI = VCC or GND, One input at VCC − 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3.6 V 3.6 V 3 V to 3.6 V 3.3 V 4.5 MIN TYP† MAX UNIT VCC−0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 ±5 10 750 µA µA µA pF V V VOL II ICC ∆ICC Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A or B TO (OUTPUT) Y VCC = 1.8 V ± 0.15 V MIN 1.2 MAX 5.3 VCC = 2.5 V ± 0.2 V MIN 1 MAX 3.2 VCC = 2.7 V MIN MAX 3 VCC = 3.3 V ± 0.3 V MIN 1 MAX 2.9 ns UNIT operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS CL = 0, f = 10 MHz VCC = 1.8 V TYP 24 VCC = 2.5 V TYP 25 VCC = 3.3 V TYP 26 UNIT pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVC08 Q1 QUADRUPLE 2 INPUT POSITIVE AND GATE SCES491B − SEPTEMBER 2003 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION RL S1 VLOAD Open GND RL TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND From Output Under Test CL (see Note A) LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI VCC VCC 2.7 V 2.7 V tr/tf ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VCC/2 VCC/2 1.5 V 1.5 V VLOAD 2 × VCC 2 × VCC 6V 6V CL 30 pF 30 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω V∆ 0.15 V 0.15 V 0.3 V 0.3 V tw Timing Input tsu Data Input VM VI VM 0V th VI VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VI Input VM VM 0V tPLH tPHL VOH Output VM VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at VLOAD (see Note B) tPZH VI Input VM VOLTAGE WAVEFORMS PULSE DURATION VM 0V VI VM VM 0V tPLZ VLOAD/2 VM VOL + V∆ tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Dec-2006 PACKAGING INFORMATION Orderable Device SN74ALVC08IDRQ1 SN74ALVC08IPWRQ1 (1) Status (1) ACTIVE ACTIVE Package Type SOIC TSSOP Package Drawing D PW Pins Package Eco Plan (2) Qty 14 14 2500 2000 Pb-Free (RoHS) TBD Lead/Ball Finish CU NIPDAU Call TI MSL Peak Temp (3) Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps use