SINGLE 2-INPUT POSITIVE-OR GATE

SN74AHC1G32 SINGLE 2-INPUT POSITIVE-OR GATE SCLS317H – MARCH 1996 – REVISED JANUARY 2000 D D D D EPIC ™ (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline Transistor (DBV, DCK) Packages DBV OR DCK PACKAGE (TOP VIEW) A B GND 1 2 3 5 4 VCC Y description The SN74AHC1G32 is a single 2-input positive-OR gate. The device performs the Boolean function Y + A ) B or Y + A • B in positive logic. The SN74AHC1G32 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS A H X L B X H L OUTPUT Y H H L logic symbol† A B 1 2 ≥1 4 Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) A B 1 2 4 Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AHC1G32 SINGLE 2-INPUT POSITIVE-OR GATE SCLS317H – MARCH 1996 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V VCC = 2 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 2 V IOL Low-level output current VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3 V VCC = 5.5 V 0 0 2 1.5 2.1 3.85 0.5 0.9 1.65 5.5 VCC –50 –4 –8 50 4 8 100 20 V V µA mA µA mA ns/V V V MAX 5.5 UNIT V ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AHC1G32 SINGLE 2-INPUT POSITIVE-OR GATE SCLS317H – MARCH 1996 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 2V IOH = –50 µA VOH IOH = –4 mA IOH = –8 mA IOL = 50 µA VOL IOL = 4 mA II ICC Ci IOL = 8 mA VI = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 3V 4.5 V 3V 4.5 V 2V 3V 4.5 V 3V 4.5 V 0 V to 5.5 V 5.5 V 5V 2 MIN 1.9 2.9 4.4 2.58 3.94 0.1 0.1 0.1 0.36 0.36 ±0.1 1 10 TA = 25°C TYP MAX 2 3 4.5 MIN 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 ±1 10 10 µA µA pF V V MAX UNIT switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL FROM (INPUT) A or B A or B TO (OUTPUT) Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN TA = 25°C TYP MAX 5.5 5.5 8 8 7.9 7.9 11.4 11.4 MIN 1 1 1 1 MAX 9.5 9.5 13 13 UNIT ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL FROM (INPUT) A or B A or B TO (OUTPUT) Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN TA = 25°C TYP MAX 3.8 3.8 5.3 5.3 5.5 5.5 7.5 7.5 MIN 1 1 1 1 MAX 6.5 6.5 8.5 8.5 UNIT ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz TYP 14 UNIT pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AHC1G32 SINGLE 2-INPUT POSITIVE-OR GATE SCLS317H – MARCH 1996 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ S1 VCC Open GND From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain S1 Open VCC GND VCC LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tsu Data Input 0V 50% VCC th 0V VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 50% VCC 0V tPLZ ≈VCC VOL + 0.3 V tPHZ VOH – 0.3 V VOH ≈0 V VOL tw VCC Input 50% VCC 50% VCC VOLTAGE WAVEFORMS PULSE DURATION Input tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 0V tPHL Output Control 50% VCC VOH 50% VCC VOL tPLH Output Waveform 1 S1 at VCC (see Note B) 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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