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SN74ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
D D D D
Member of the Texas Instruments Widebus Family Compatible With IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Includes D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data Two Boundary-Scan Cells Per I/O for Greater Flexibility
D
SCOPE Instruction Set – IEEE Std 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ – Parallel Signature Analysis at Inputs With Masking Option – Pseudorandom Pattern Generation From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes
PM PACKAGE (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6
1A2 1A1 1OE GND 1SAB 1CLKAB TDO V CC TMS 1CLKBA 1SBA 1DIR GND 1B1 1B2 1B3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7
description
This scan test device with a 18-bit bus transceiver and register is a member of the Texas Instruments SCOPE testability IC family. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port (TAP) interface.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
2A7 2A8 2A9 GND 2OE 2SAB 2CLKAB TDI VCC TCK 2CLKBA 2SBA GND 2DIR 2B9 2B8
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SN74ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
description (continued)
In the normal mode, this device is an 18-bit bus transceiver and register that allows for multiplexed transmission of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and registers. Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses. Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74ABT18646. In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions, such as parallel signature analysis on data inputs and pseudorandom pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. ORDERING INFORMATION
TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 85°C LQFP – PM Tray SN74ABT18646PM ABT18646 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
FUNCTION TABLE (normal mode, each 9-bit section) INPUTS OE X X H H L L L DIR X X X X L L H CLKAB ↑ X ↑ L X X X CLKBA X ↑ ↑ L X X X SAB X X X X X X L SBA X X X X L H X A1–A9 Input Unspecified† Input Input disabled Output Output Input DATA I/O B1–B9 Unspecified† Input Input Input disabled Input Input disabled Output OPERATION OR FUNCTION Store A, B unspecified† Store B, A unspecified† Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
L H L X H X Input disabled Output Stored A data to B bus † The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X L CLKBA X X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X ↑ X ↑ ↑ ↑ STORAGE FROM A, B, OR A AND B
SAB X X X
SBA X X X
OE L L
Figure 1. Bus-Management Functions
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
BUS A DIR L H
BUS A
SN74ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
functional block diagram
1OE 1DIR 1CLKBA 62 53 55
Boundary-Scan Register
1SBA 54 59 1CLKAB 60 1SAB
C1 1D
1A1
63
C1 1D 1 of 9 Channels
51
1B1
2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB
21 30 27 28 23 22
C1 1D
2A1
10
C1 1D 1 of 9 Channels
40
2B1
Bypass Register
Boundary-Control Register Identification Register
VCC TDI 24 VCC TMS TCK 56 26
58
Instruction Register
TDO
TAP Controller
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI IOH IOL ∆t/∆v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate 0 4.5 2 0.8 VCC –32 64 10 MAX 5.5 UNIT V V V V mA mA ns/V
TA Operating free-air temperature –40 85 °C NOTE 3: All unused inputs of the device must be held
