QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 D D D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH, 64-mA IOL) Ioff and Power-Up 3-State Support Hot Insertion D D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) SN54ABT125 . . . FK PACKAGE (TOP VIEW) 1OE 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1 14 13 12 11 10 9 VCC 1A 1Y 2OE 2A 2Y 2 3 4 5 6 7 8 4OE 4A 4Y 3OE 3A 1Y NC 2OE NC 2A 1A 1OE NC VCC 4OE 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 SN54ABT125 . . . J OR W PACKAGE SN74ABT125 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) SN74ABT125 . . . RGY PACKAGE (TOP VIEW) 4A NC 4Y NC 3OE GND NC – No internal connection description/ordering information The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PDIP – N QFN – RGY –40°C to 85°C SOIC – D SOP – NS SSOP – DB TSSOP – PW CDIP – J –55°C to 125°C CFP – W LCCC – FK PACKAGE† Tube Tape and reel Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74ABT125N SN74ABT125RGYR SN74ABT125D SN74ABT125DR SN74ABT125NSR SN74ABT125DBR SN74ABT125PWR SNJ54ABT125J SNJ54ABT125W SNJ54ABT125FK TOP-SIDE MARKING SN74ABT125N AB125 ABT125 ABT125 AB125 AB125 SNJ54ABT125J SNJ54ABT125W SNJ54ABT125FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Y GND NC 3Y 3A 3Y 1 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z logic diagram (positive logic) 1OE 1A 1 2 3 3OE 1Y 3A 10 9 8 3Y 2OE 2A 4 5 6 4OE 2Y 4A 13 12 11 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 recommended operating conditions (see Note 4) SN54ABT125 MIN VCC VIH VIL VI IOH IOL ∆t/∆v ∆t/∆VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature 200 –55 125 0 4.5 2 0.8 VCC –24 48 10 200 –40 85 0 MAX 5.5 SN74ABT125 MIN 4.5 2 0.8 VCC –32 64 10 MAX 5.5 UNIT V V V V mA mA ns/V µs/V °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL Vhys II IOZPU IOZPD IOZH IOZL Ioff ICEX IO‡ ICC VCC = 4 5 V 4.5 TEST CONDITIONS II = –18 mA IOH = –3 mA IOH = –3 mA IOH = –24 mA IOH = –32 mA IOL = 48 mA IOL = 64 mA 100 VCC = 0 to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V VCC = 2.1 V to 5.5 V, VCC = 0, VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0, VI = VCC or GND Data inputs Control inputs Ci VCC = 5.5 V, One input at 3.4 V, , Other inputs at VCC or GND VO = 0.5 V, OE ≥ 2 V VI or VO ≤ 4.5 V Outputs high VO = 2.5 V Outputs high Outputs low Outputs disabled Outputs enabled Outputs disabled –50 –100 1 24 0.5 ±1 ±50 ±50 10 –10 ±100 50 –200§ 250 30 250 1.5 0.05 1.5 3 –50 50 –200§ 250 30 250 1.5 0.05 1.5 –50 ±1 ±50 ±50 10 –10 ±1 ±50 ±50 10 –10 ±100 50 –200§ 250 30 250 1.5 0.05 1.5 pF pF mA MIN 2.5 3 2 2* 0.55 0.55* 0.55 0.55 TA = 25°C TYP† MAX –1.2 2.5 3 2 2 V mV µA µA µA µA µA µA µA mA µA mA µA SN54ABT125 MIN MAX –1.2 2.5 3 V SN74ABT125 MIN MAX –1.2 UNIT V VOH ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Co 7 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This limit may vary among suppliers. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER tPLH† tPHL† tPZH† tPZL† tPHZ tPLZ† FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN 1 1 1 1 1 1 TYP 3.2 2.5 3.6 2.5 3.8 3.3 MAX 4.6 4.6 5 6.2 5.4 5.3 SN54ABT125 MIN 1 1 1 1 1 1 MAX 6 6.2 6 7.5 6.3 6.5 SN74ABT125 MIN 1 1 1 1 1 1 MAX 4.9 4.9 5.9 6.8 6.2 6.2 ns ns ns UNIT A Y Y Y OE OE † This limit may vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION 500 Ω S1 7V Open GND 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFOR